Power on Reset IP, Input: 1.0V, UMC 90nm SP process
Vrr=0.67V Vfr=0.63V, input 1.0V, Core type, Power On Reset (with Self-Test Circuit), UMC 90nm SP/RVT Logic Low-K process.
- UMC
- 90nm
- SP
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Power on Reset IP, Input: 1.0V, UMC 90nm SP process
Vrr=0.67V Vfr=0.63V, input 1.0V, Core type, Power On Reset (with Self-Test Circuit), UMC 90nm SP/RVT Logic Low-K process.
PLL (Spread Spectrum) IP, UMC 40nm LP process
Input clock:8MHz, output clock range:720 ~ 1680MHz wide-range SSCG, UMC 40nm LP process.
PLL (Spread Spectrum) IP, UMC 40nm LP process
Input clock range:5 ~ 1280MHz, output clock range:15.625 ~ 2000MHz wide-range SSCG, UMC UMC 40nm LP/LVT Low-K Logic process.
PLL (Spread Spectrum) IP, Input: 5MHz - 1280MHz, Output: 15.625MHz - 2000MHz, UMC 55nm LP process
Input 20M-135MHz, output 20M-135MHz SSCG, UMC 0.18um Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm SP process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.18um GII Logic process.
Input 5M-200MHz, output 25M-400MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
Input 5M-200MHz, output 12.5M-200MHz, frequency synthesizable PLL, UMC 0.13um LL Logic/FSG process.
Input 5M-100MHz, output 62.5M-1000MHz, frequency synthesizable PLL with power/ground pad, UMC 0.13um HS/FSG Logic process.
Input 5M-100MHz, output 62.5M-1000MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, , Output: 20MHz - 300MHz, UMC 0.25um process
Input 5M-100MHz, output 20M-300MHz, frequency synthesizable PLL, 0.25um Logic process.
PLL (Frequency Synthesizer) IP, Input: 4MHz - 200MHz, Output: 20MHz - 400MHz, UMC 0.18um G2 process
Input 4M-200MHz, output 20M-400MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
Input 45k-60KHz, output 81M- 132MHz, PLL, UMC 0.11um HS/FSG Logic process.
UMC 0.13um HS/FSG process PLL for DDR2.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HPM process
Input 25M-50MHz, output 1000M-2000MHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HPM process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 200MHz, Output: 1GHz -1.5GHz, UMC 90nm SP process
Input 25M-200MHz, output 1000M-1500MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HPM process
Input 20M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HPM process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 28nm HLP process
Input 20M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HLP process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.