Overview
TRC6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit Interface) and SGMII interfaces. Fig. 1 shows the top-level block diagram of this module in the XAUI mode where these 4 channels can receive and transmit data synchronously at the rate of 3.125Gbps each. Fig. 2 shows the top-level block diagram of the module in RXAUI mode where 2 channels are disabled and the other 2 operate synchronously at the rate of 6.25Gbps each. The 4 channels can also operate as 4 independent channels.
Depending on the application, each transmitter can serialize 8, 10, 16 or 20 bit parallel data to a differential serial output and each receiver can de-serialize a differential serial input to 8, 10, 16 or 20 bit parallel output. A common block including a TXPLL provides clocks to the serializers in all channels. To improve signal integrity the common block also includes a calibration circuit providing control signals to make the transmitter output resistance and the receiver input resistance within 50?±10%.
Fig 3. Shows the block diagram of each channel. At the RX side the serial input data goes through the input stage with linear equalization. The Clock and data recovery (CDR) circuit receives the data. It then extracts the clock, and provides the clock and the retimed data to the de-serializer. The de-serializer converts the serial data to 8, 10, 16 or 20bit parallel data with corresponding rx-clk.
There is an eye-monitor block to measure the height of the signal going to the CDR. When enabled, the information about the height of the signal will be sent out through 16 bit parallel data line.
A Loss Of Signal (LOS) detector also detects if there are valid data at the input.
For the boundary scan testing there is a AC JTAG block at the input providing data to the core in the test mode. At the TX side the serialized data goes through the output driver. To further improve the jitter performance there are programmable pre-emphasis capabilities at the transmitter output stage.
In addition near end and far end serial loopback are implemented to be able to test the channel.
Learn more about Multi-Protocol PHY IP core
Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.
Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.
Steven Brown
The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.
