TSMC Preps 10nm, Tunes 16nm
10nm needs new flow, Xilinx will skip it
Rick Merritt, EETimes
9/17/2015 05:00 PM ED
SANTA CLARA, Calif. -- TSMC will start early production on a 10nm process this year and 7nm in 2017, executives said in a road map update here. In between, the foundry giant will release a cost-reduced version of its 16nm process next year and a broad portfolio of specialty processes for the Internet of Things, automotive and sensors.
The road map suggests TSMC could leapfrog Intel to producing 10nm chips, although naming conventions for nodes these days hide the underlying details of the processes. What's more clear is TSMC has gotten off to a slow start with its 16nm FinFET process with close partners such as Xilinx saying they have taped out but not yet shipped their first chip in the process. Xilinx also plans to skip TSMC’s 10mn process in favor of its 7nm node, a significant choice given Xilinx typically acts as a logic driver for new TSMC nodes.
To read the full article, click here
Related Semiconductor IP
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
Related News
- Synopsys Tools Achieve TSMC Certification for 16-nm FinFET+ Process and Entered 10-nm FinFET Collaboration
- TSMC Certifies Synopsys Design Tools for 16-nm FinFET Plus Production and for 10-nm Early Design Starts
- TSMC Outlines 16nm, 10nm Plans
- TSMC plans 1.6nm process for 2026
Latest News
- ASICLAND Partners with Daegu Metropolitan City to Advance Demonstration and Commercialization of Korean AI Semiconductors
- SEALSQ and Lattice Collaborate to Deliver Unified TPM-FPGA Architecture for Post-Quantum Security
- SEMIFIVE Partners with Niobium to Develop FHE Accelerator, Driving U.S. Market Expansion
- TASKING Delivers Advanced Worst-Case Timing Coupling Analysis and Mitigation for Multicore Designs
- Efficient Computer Raises $60 Million to Advance Energy-Efficient General-Purpose Processors for AI