Why RISC-V + Blockchain Is the Conversation I’ve Been Waiting to Have
By Daniela Barbosa, GM of Decentralized Technologies at the Linux Foundation & Executive Director, LF Decentralized Trust
EETimes | October 14, 2025
The open RISC-V ISA has always been about freedom and flexibility in hardware design. Now a compelling new use case gives developers a software-only abstraction layer, taking privacy and flexibility to new heights.
There are rarely moments in technology when two open ecosystems simply ‘click’ into place. Yet here I am, feeling like the officiant between two such entities: the open hardware standard RISC-V, and the shared, immutable digital ledger that is blockchain.
Blockchain is no longer an experiment or a buzzword; it’s becoming part of the world’s critical infrastructure.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related News
- LTSCT and Andes Technology Sign Strategic IP Licensing Master Agreement to accelerate RISC-V Based Advanced Semiconductor Solutions
- Syntacore upgrades its SCR RISC-V IP: Packed-SIMD, Zicond and Zimop Extensions
- SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink™ Fusion
- Nuclei Announces Strategic Global Expansion to Accelerate RISC-V Adoption in 2026
Latest News
- PQSecure Collaborates with George Mason University on NIST Lightweight Cryptography Hardware Research
- Omni Design Technologies Advances 200G-Class Co-Packaged Optics IP Portfolio for Next-Generation AI Infrastructure
- Global Annual Semiconductor Sales Increase 25.6% to $791.7 Billion in 2025
- Fabless Startup Aheesa Tapes Out First Indian RISC-V Network SoC
- SmartDV and Mirabilis Design Announce Strategic Collaboration for System-Level Modeling of SmartDV IP