Phylinks Taps Nabil Takla as Chairman
SAN FRANCISCO -- December 14, 2006
-- Phylinks, Ltd., an innovator of IP cores for the design of physical layer (PHY) high-speed serial interfaces, announced today that it has appointed Nabil Takla, the CEO and founder of Innovative Semiconductor, as chairman of the Phylinks board of directors. Takla's business acumen and marketing expertise will provide a valuable addition to the Phylinks team, which thus far has focused on building a broad portfolio of IP products for SoCs used in a variety of communications and computing applications.
In particular, Nabil Takla's experience in mixed-signal IP cores will be a valuable addition to marketing Phylinks' design-for-test architecture, which is built from the ground up to address the complex issues of testing high speed mixed-signal designs. While Takla is retaining his position as CEO of Innovative Semiconductors, he will play a hands-on role in bringing to market Phylinks' products.
"Phylinks is primed for success under the direction of Nabil Takla, who brings over 30 years of experience in business, management, marketing, and technology to the Phylinks board of directors," said Antony Sou, chief operating officer and founder of Phylinks. "Phylinks has developed a robust design-for-test architecture, and Nabil will be an ideal resource on the business side as we bring our cores to market and grow the company."
"The high-speed performance of SATA and PCI Express creates new design challenges, and Phylinks is meeting those challenges with rigorous testing and compatibility," said Philip Hodgett, chief technology officer and founder of Phylinks. "With the added leadership, we can sharpen our focus even further on developing new breakthroughs in IP technology, backed by unmatched reliability and customer service."
"Phylinks is the right company at the right time to deliver this technology to today's market, and their strong engineering team and architecture convinced me to become involved in their future in any way that I can," said Nabil Takla, CEO and chairman of the board of Phylinks. "Phylinks' design-for-test architecture brings predictability to the SoC design process by delivering IP cores that are painstakingly tested and precisely built to the latest industry standard specifications."
About Phylinks IP Cores
Phylinks IP cores are optimized for minimum area, low power, extensive testing, and interoperability with a variety of third-party solutions. This makes them ideal for use in the development of high-performance communications, PC, mass storage, optical and server applications.
Phylinks IP cores are designed with a particular emphasis on test and manufacturing. An extensive suite of test features makes it easy for designers to test, characterize and manufacture reliable products. Phylinks' innovative architecture effectively tackles the complex issues of testing high-speed mixed-signal designs.
About Nabil Takla
Nabil Takla is the founder and CEO of Innovative Semiconductors, Inc., a mixed-signal IP company, and has worked with some of the world's leading semiconductor manufacturers to build millions of chips used in high-speed serial interface applications, particularly in the areas of USB, FireWire and digital video encode/decode.
About Phylinks
Phylinks, Inc. provides a portfolio of IP Cores for the design of physical layer (PHY) high speed serial interfaces. Phylinks cores can be implemented in a variety of chip designs for use in advanced PCs, PC peripherals, servers, and 3G communications devices. Phylinks was founded in December 2005 by Antony Sou and Philip Hodgett -- two experienced mixed-signal designers with over 40 years of combined experience. In 2006, Nabil Takla, a mixed-signal IP expert who is also the CEO of Innovative Semiconductors, Inc., invested in Phylinks and joined the management team as CEO. Phylinks has offices in Manchester UK, and San Francisco, California. For more information, visit www.phylinks.com.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Nabil Takla, Innovative Semi CEO, hatches incubator fund for Asia, eastern Europe
- Sequence taps Qualcore for SoC center in India
- Sharp taps Parthus' Java accelerator for system-on-chip products
- Toshiba taps inSilicon's USB 2.0 core for system-on-chip designs
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers