PACT announced beta availability of its XPP Vectorizing C-Compiler (XPP-VC) technology
C way to reconfigurable ASICs
By David Larner, Embedded Systems
October 4, 2001 (10:51 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011004S0034
PACT announced beta availability of its XPP Vectorizing C-Compiler (XPP-VC) technology. This is designed to allow developers to create "virtual reconfigurable ASICs" using existing C language source code as opposed to hardware programming in Verilog/VHDL or proprietary tools.
Related Semiconductor IP
- USB 20Gbps Device Controller
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- AGILEX 7 R-Tile Gen5 NVMe Host IP
Related News
- Axys models new ARM core, Pact speeds up XPP
- PACT XPP Technologies teams with Accent to offer SOC Design Services and Application Platforms for XPP-Based Solutions
- QuickLogic and PACT team to develop Multi-Processor programmable SoC solutions for wireless and multimedia applications
- PACT announces the Smart Media XPP Package for Multi-Standard Video Codecs
Latest News
- BrainChip Expands Global Reach, Announces Akida Boards and AI Development Kits Available at DigiKey
- Qualitas Semiconductor Successfully Demonstrates Live UCIe PHY IP at AI Infra Summit 2025
- Silicon Creations Announces 1000th Production FinFET Tapeout at TSMC and Immediate Availability of Full IP Library on TSMC N2 Technology
- Intel and NVIDIA to Jointly Develop AI Infrastructure and Personal Computing Products
- Comcores MACsec IP is compliant with the OPEN Alliance Standard