Chelsio Expands Terminator 5 ASIC Product Line
Price Optimized SKUs Target Datacenter and Cloud Applications
SUNNYVALE, Calif., January 21, 2015 – Chelsio Communications, Inc., the leading provider of Ethernet Unified Wire Adapters and ASICs, today announced the launch of four new SKUs in its Terminator 5 (T5) ASIC product line, the fifth generation of Chelsio's high performance Ethernet silicon technology and a recognized leader in performance, capabilities and features. T5 is a highly integrated, hyper-virtualized 10/40GbE controller with full offload support of a complete Unified Wire solution comprising NIC, TOE, iWARP RDMA, iSCSI, FCoE, NAT, NVGRE and VXLAN support, Security and Filtering, and Traffic Analytics and Management. T5 provides no-compromise performance with high packet processing capacity, sub-microsecond hardware latency and high bandwidth, limited only by the PCIe Gen3 bus. Furthermore, it scales to true 40 Gigabit line rate operation from a single TCP connection to thousands of connections, and allows simultaneous low latency and high bandwidth operation thanks to multiple physical channels through the ASIC.
The new SKUs expand the reach of T5 ASICs into the Datacenter and Cloud scale applications. Chelsio is announcing the immediate availability of the following products:
- T5ASIC10G – 4x10Gb with complete feature-set
- T5ASIC40G – 2x40Gb or 4x10Gb with complete feature-set
- T5ASIC10G-SO – 4x10Gb with stateless offload only
- T5ASIC40G-SO – 2x40Gb or 4x10Gb with stateless offload only
All products can be used in single chip configuration, without external memories, to provide full server adapter NIC functionality, including traffic management and QoS, filtering, load balancing, and NAT. A unified software suite supports all the 4 SKUs, and is available in source form, without a license fee. All 4 products are pin compatible with each other and with the currently shipping T5 ASIC.
Given the high integration of T5, the ability to concurrently run all the different protocols at industry leading performance levels, and the rich feature set that addresses all the key Ethernet market segments, the silicon enables OEMs to converge on a single vendor for all their connectivity needs, with price-optimized products to match the different requirements for each.
Designed for high performance clustering, storage and data networking, T5 enables fabric consolidation by simultaneously offloading TCP/UDP/IP sockets, RDMA and storage traffic at wire speed, thereby allowing InfiniBand and FibreChannel applications to run unmodified and concurrently over standard
Ethernet networks. By eliminating the need for InfiniBand or FibreChannel adapters, cabling, switches and gateways, T5 offers tremendous cost and operational savings.
With a specific design focus on low latency and small packet processing performance, T5 also enables a new performance milestone for high frequency trading and other latency sensitive applications.
"We are excited to launch four new products in the Terminator 5 ASIC line today. These come as a response to our customers' desire to deploy T5 in a variety of new areas which benefit from its leading performance and feature set," said Kianoosh Naghshineh, CEO and president of Chelsio Communications, Inc. "Chelsio's ASIC product line now addresses a uniquely wide range of applications, from high performance storage, to clustering, clouds and datacenters."
"Widely recognized as a performance and feature leader, Chelsio is now addressing lower price points that meet requirements for hyper-scale networks," said Bob Wheeler, Principal Analyst at The Linley Group. "The expanded T5 ASIC product line should be welcomed by customers wishing to access Chelsio's technology at these new scale-optimized price points."
T5 Architectural Features The T5 ASIC is built around a highly scalable and programmable protocol-processing engine. Much of the processing of the offloaded protocols is implemented in microcode running on a proprietary pipelined data-flow engine. The pipeline supports cut-through operation for both transmit and receive paths for minimum latency, and the transport processor is designed for wire-speed operation at small packet sizes, regardless of the number of TCP connections.
Some key features of the ASIC:
- PCI Express v3.0 x8 host interface
- 2xDDR-3 memory interfaces
- 4x10G/1G or 2x40G Ethernet ports
- Designed for very low latency, high bandwidth and high packet processing rate
- NIC/TOE/iWARP RDMA/iSCSI/FCoE/NAT offload
- TOE/iWARP RDMA/iSCSI/FCoE port-to-port, and adapter-to-adapter failover
- SR-IOV 8PF/128VF + NVGRE/VXLAN, 802.1Qbg/802.1Qbr network virtualization
- Integrated OpenFlow ready virtual Ethernet switch
- T10-DIF/DIX flexible end-to-end protection support for both FCoE and iSCSI
- Filtering, Classification, Traffic Management, and Traffic Capture offload
Availability and Pricing The new T5 products are available today. For pricing, contact Chelsio at +1-408-962-3600, or visit the company at www.chelsio.com.
About Chelsio Communications, Inc.
Chelsio is a leading technology company focused on solving high performance networking and storage challenges for virtualized enterprise data centers, cloud service installations, and cluster computing environments. With its fifth generation protocol acceleration technology, Chelsio is enabling hardware and software solutions including Unified Wire Ethernet network adapter cards, unified storage software, high performance storage gateways, unified management software, bypass cards, and other solutions focused on specialized applications. Visit the company at www.chelsio.com.
Related Semiconductor IP
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
- High Speed Ethernet 200G/400G/800G MAC
Related News
- Chelsio Launches Terminator Core IP
- Sidense Raises $5 million in Venture Capital to Expand Product Development
- Chelsio Communications Licenses Tensilica's Xtensa LX Customizable Dataplane Processor Core for 10 Gigabit Ethernet
- Cypress to Showcase PSoC(R) 5 Architecture and PSoC Creator(TM) IDE for ARM(R)-Based Design
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers