Axiomise 推出适用于 RISC-V 处理器的新兴formalISA 应用程序
LONDON –– June 1, 2023 –– Axiomise, the leading provider of cutting-edge formal verification solutions that include training, consulting, services and custom apps, today launched its next-generation formalISA® app with open-source, formally verified RISC-V processors such as cv32e40p and WARP-V.
Also announced today is a new RISC-V Studio Portal with real-world formalISA applications and product demonstrations to help the RISC-V ecosystem understand the necessity of exhaustive formal and the kind of bugs that can be caught with formal methods.
“We are excited to share the app launch in conjunction with a new studio portal with real-world applications of formalISA and product demos,” remarks Dr. Darbari. “The app will enable the wider ecosystem of RISC-V to see why exhaustive formal verification is a necessity and what kind of bugs can be caught with formal methods. FormalISA app is a powerful offering in realizing our vision of making formal normal. Axiomise has the tools and the skills to become the ‘go to’ RISC-V Verification expert.”
Dr. Darbari and his team will be at the RISC-V Summit Europe to demonstrate formal lSA in Bay 7 from Tuesday, June 6, to Thursday, June 8, at Hotel Barcelo Sants in Barcelona, Spain.
About formalISA
Axiomise’s formalISA is a push-button formal verification solution used for architectural and micro-architectural verification of RISC-V processor cores. Initially launched four years ago, it has been used to formally verify numerous open-source and commercial RISC-V processors by identifying deep corner-case bugs and mathematically proving the absence of bugs on complex out-of-order and in-order cores.
A state-of-the-art proof status dashboard captures reporting and coverage information and provides full automation, saving time and cost. FormalISA is powered by i-RADAR®, and a reporting and coverage solution called SURF.
Formal ISA is available now. Pricing is available upon request.
About Axiomise
Axiomise is accelerating formal verification adoption through its unique combination of training, consulting, services and specialized verification solutions for RISC-V. Axiomise was founded by Dr. Ashish Darbari, FBCS, FIETE, DPhil (Oxford), who has been a formal verification practitioner for more than two decades with 60 patents in formal verification and over 70 publications.
Related Semiconductor IP
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
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