USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
XtremeSilica’s USB 3.2 Verification IP offers a comprehensive solution for validating designs based on the USB 3.2 specification.
USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
MSquare's USB 3.2 PHY IP is designed based on the USB 3.2 Gen2x1 and USB 2.0 specifications from the USB Implementers Forum and d…
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
All USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps are supported by the USB 3.2 Gen2X1 transceiver IP.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 12FFC
All USB 3.2 Gen2X1 host and peripheral applications are supported up to 10Gbps by the USB 3.2 Gen2X1 transceiver IP.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 7FF
The USB 3.2 Gen2X1 transceiver IP offers all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.1 Base Specification with support…
USB 3.2 Gen2 PHY IP, Silicon Proven in UMC 28HPC
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum.
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.
The USB3.2 Verification IP provides an effective & efficient way to verify the components connected with USB3.2 interface of an I…
Super-Speed Plus USB 3.2 Hub Controller
USB3.2 SuperSpeed Hub The Super Speed Plus USB bus is implemented as a separate dual-simplex dual lane data path consisting of tw…
USB 3.0/3.1/3.2/SSIC Verification IP
USB 3.0/3.1/3.2 Verification IP provides a smart way to verify the USB 3.0/3.1/3.2 component of a SOC or a ASIC.
MIPI GbD USB Verification IP provides a smart way to verify the MIPI GbD USB component of a SOC or a ASIC.
The USB Super-Speed+ PHY IP is a compact and power-efficient interface solution that fully supports the USB 3.2 Gen1 and Gen2 spe…
USB-C 3.2 SS/SSP PHY in Type-C in Samsung (SF4X, SF4E, SF2)
The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum.
USB-C 3.2 SS/SSP PHY in Type-C in TSMC (N7, N6, N5, N3E)
The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum.
Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.
USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …