The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standa…
- Symmetric Crypto
The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standa…
Security Protocol Accelerator for SM3 and SM4 Ciphers
Complex system-on-chip (SoC) requirements can include security at various application layers.
Security Protocol Accelerator for SM3 and SM4
SM3 and SM4 are commercial cryptographic standards issued and regulated by the Chinese Office of State Commercial Cryptography Ad…
SM4 (former name “SMS4”) is a cryptographic standard published by the Office of State Commercial Cryptography Administration (OSC…
The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of Chi…
Cryptographic engine using the DES, Triple-DES or AES
The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
Symmetric Cryptographic Intel® FPGA IP
The Symmetric Cryptographic Intel® FPGA IP is a hard IP core implementing AES and SM4 encryption and decryption.
Embedded Hardware Security Module (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
The RT-64x Embedded Hardware Security Module (Root of Trust) family are fully programmable, ISO 26262 ASIL-B hardware security co…
High-speed Inline Cipher Engine
The ICE-IP-338 (EIP-338) Inline Cipher Engine is a scalable, high-performance, multi-stream inline cryptographic engine that offe…
Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
The ICE-IP-338 (EIP-338) Inline Cipher Engine is a scalable, high-performance, multi-stream inline cryptographic engine that offe…
Embedded HSM Family (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
The Rambus RT-64x Embedded Hardware Security Module (Root of Trust) family are fully programmable, ISO 26262 ASIL-B hardware secu…
The MACsec Intel® FPGA IP core implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018) as fully c…
Inline cipher engine with AXI, for memory encryption
Modern computing architectures must address increasing concerns regarding off-chip data confidentiality.
Multipurpose Security Protocol Accelerator
The Multipurpose Security Protocol Accelerator (SPAcc) offers designers unprecedented configurability to address the complex secu…
VeriSyno provides a flexible and configurable security IP solution, which includes common symmetric encryption algorithms, random…
TLS 1.3 Compliant Crypto Coprocessor
PUFcc7 is the latest revision of the vendor’s high-security Crypto Coprocessor.
Multipurpose Security Protocol Accelerator - Functional Safety ASIL B support
The Multipurpose Security Protocol Accelerator (SPAcc) offers designers unprecedented configurability to address the complex secu…
Network Security Crypto Accelerator
The Network Security Crypto Accelerator is a hardware IP core platform that accelerates cryptographic operations in System-on-Chi…
Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
The Protocol-IP-196 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, DTLS, 3GPP and MACse…
PUFcc is a novel high-security Crypto Coprocessor.