XSPI (Expanded Serial Peripheral Interface) Synthesizable Transactor

XSPI (Expanded Serial Peripheral Interface) Synthesizable Transactor provides a smart way to verify the XSPI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's XSPI (Expanded Serial Peripheral Interface) Synthesizable Transactor is fully compliant with standard XSPI Specification and provides thefollowing features.

• Follows XSPI basic specification as defined in JEDEC eXpanded Serial Peripheral Interface (xSPI)for Non Volatile Memory Devices
• Supports Master and Slave Mode
• Supports 4-wire,7-wire,11-wire interface
• Supports data width upto 8 bits
• Supports bus width of 1 bit ,4 bits and 8 bits
• Supports baud rate selection
• Supports internal clock division check
• Supports clock polarity and CPHA selections
• Supports single and burst transfer mode
• Supports single,dual,quad mode and Octal bus width operation
• XSPI Slave can be configured as standard device or can use FIFO for data passing
• Master contains rich set of commands for both standard device and FIFO model mode

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the XSPI testcases
• Examples showing how to connect and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and functions used in verification env
• Documentation also contains User's Guide and Release notes