Vendor:
Cadence Design Systems, Inc.
Category:
SPI / QSPI XSPI
Simulation VIP for SPI
This Cadence® Verification IP (VIP) provides support for the SPI protocol.
Overview
This Cadence® Verification IP (VIP) provides support for the SPI protocol. The SPI VIP provides a complete bus functional model (BFM) and integrated automatic protocol checks. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the Cadence SPI VIP helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence VIPs run on all major simulators and supports the SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported Specifications: Samsung SPI based on the Exynos 5250 spec Revision 1.00, Motorola SPI based on Block Guide V03.06 and SafeSPI SPI for Automotive Safety V0.15.
Key features
- Full Duplex
- Simultaneous transfer from Manager and Subordinate
- Variable Size Shift Registers
- 8, 16, and 32-bit shift register for Tx and Rx
- Variable Bus Sizes
- 8, 16, and 32-bit bus interface
- Tx and Rx FIFOs
- Two independent 32-bit wide transmit and receive FIFOs
- Manager/Subordinate Modes
- Manager-mode and Subordinate-mode
- Rx Only
- Receive-without-transmit operation
- Slave Select Output
- SS output
- Mode Fault Error
- Mode fault error flag with CPU interrupt capability
- Clock Polarity
- Serial clock with programmable polarity and phase
- Control on Wait Mode
- Control of SPI operation during wait mode
- Bidirectional Mode
- One serial data pin for the interface with external device
- Low Power Mode
- Run mode, wait mode and stop mode
- Timing Delays
- Timing parameters for SCK and SS signals
Block Diagram
Simulation VIP for SPI block diagram
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
Simulation VIP for SPI
Vendor
Cadence Design Systems, Inc.
Type
Verification IP
Provider
Cadence Design Systems, Inc.
HQ:
USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.
Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster.
The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements.
Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Learn more about SPI / QSPI XSPI IP core
Unleashing the Power of Communication: Exploring the XSPI Protocol and Arasan Chip Systems' XSPI IP Portfolio
Frequently asked questions about SPI / QSPI / xSPI IP cores
What is Simulation VIP for SPI?
Simulation VIP for SPI is a SPI / QSPI XSPI IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.