Vendor: Arasan Chip Systems Inc. Category: UniPro

UniPro℠ Controller IP Core

To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to de…

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Overview

To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open standards for interfaces to mobile application processors. The Unified Protocol (UniPro) is one in a family of standards addressing the mobile market.

The UniPro Controller IP core is fully compliant with the UniPro specification version 1.6 and supports the physical adapter layer of the M-PHY® specification. MIPI UniPro is a high-performance, chip-to-chip, serial interconnect bus for mobile applications. Designed to support up to 5Gbps per data lane, it is scalable from one to four bidirectional lanes. To achieve optimal performance the Arasan UniPro Controller implements the following layers in hardware:

  • Physical adapter layer
  • Data link layer
  • Network layer
  • Transport layer

TC0 and TC1 traffic classes are handled on a priority-based transmission, and additional features include support of multiple power modes, error detection and handling, and data transmission preemption.

Unique to the Arasan controller is optional support that utilizes end-to-end flow control within UniPro to maximize transmission throughput and efficiency. Designed specifically for applications such as mobile phones, portable handheld media players, and mobile terminals, UniPro provides the high-speed connectivity needed between the applications processor and application devices such as wireless modules, graphics processors, multimedia accelerators, and storage subsystems. Targeted specifically for mobile phones, UniPro will be the high-speed chip connection of choice moving forward.

Key features

  • MIPI UniPro Compliant
  • MIPI M-PHY Version 3.0
  • Multi-lane: one to four
  • Up to 5Gbps per lane
  • Package base protocol
  • Device Independent
  • Priority-based traffic classes (TC0 & TC1)
  • Preemption support during data frame transmission
  • Autonomous error detection and handling
  • Multiple power modes

Layer Support

  • PHY Adapter (L1.5)
  • Data Link (L2)
  • Network Layer (L3)
  • Transport Layer (L4)

Interfaces

  • AHB
  • AXI
  • OCP
  • Custom

Block Diagram

UniPro℠ Controller IP Core block diagram

Benefits

  • Fully compliant core with proven silicon
  • Premier direct support from Arasan IP core designers
  • Easy-to-use industry standard test environment
  • Unencrypted source code allows easy implementation
  • Customer training available
  • Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglas

What’s Included?

  • RMM-compliant synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
UniPro℠ Controller IP Core
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Provider

Arasan Chip Systems Inc.
HQ: USA
Arasan Chip Systems, is a leading provider of IP for mobile storage and mobile connectivity interfaces with over a billion chips shipped with our IP. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP, Analog Mixed Signal PHY IP, Verification IP, HDK, and Software. Arasan has a focused product portfolio targeting mobile SoCs. The term Mobile has evolved over our two-decade history to include all things mobile – starting with PDA’s in the mid 90’s to smartphones to today’s Automobiles, Drones, and IoT. Arasan is at the forefront of this evolution of “Mobile” with its standards-based IP at the heart of Mobile SoCs.
Contact Arasan Chip Systems Inc.

Learn more about UniPro IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Vertically Integrated MIPI Solutions

The emerging MIPI standards are designed to ensure interoperability among devices and software that are used in products for the exploding hand-held market. The standards facilitate the interconnection of multiple, mixed-signal integrated circuit devices on a single hand-held product. Use of the standards ensures low power, low pin count and interoperability of all the devices in the system and easy integration.

Frequently asked questions about UniPro IP cores

What is UniPro℠ Controller IP Core?

UniPro℠ Controller IP Core is a UniPro IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this UniPro?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UniPro IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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