Vendor: Cadence Design Systems, Inc. Category: UniPro

Simulation VIP for MIPI UniPro

Best-in-class MIPI® UniPro Verification IP for your IP, SoC, and System-Level Design Testing In production since 2011 on dozens o…

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Verification IP View all specifications

Overview

Best-in-class MIPI® UniPro Verification IP for your IP, SoC, and System-Level Design Testing

In production since 2011 on dozens of production designs.

Incorporating the latest protocol updates, the mature and comprehensive Cadence Verification IP (VIP) for the MIPI® UniProsm Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for UniPro helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specifications: MIPI UniPro v1.6, v1.8, v2.0, and v3.0 and M-PHY v4.0, v4.1, v5.0, and v6.0.

Key Features

The following table describes key features from the specifications that are implemented in the VIP for UniPro:

Feature Name

Description

Serial and RMMI interfaces
  • Supports serial and RMMI interfaces (downstream)

CPORT signal interface
  • Supports CPORT signal interface (upstream)

All layers supported
  • Supports PHY adapter, data link, network, and transport layers

Built-in sequences
  • PA link start up, (re-)initialization, configuration, error-recovery, and hibernate enter/exit sequences

Data link layer
  • Supports DLL initialization, TC0 and TC1, flow control, and acknowledgment mechanisms

Transport layer
  • Supports TL connection management and addressing, segmentation and reassembly,
    end-to-end flow control, and multi-CPORT arbitration

Lane capabilities
  • Supports up to four lanes, PWM G1-G7, HS G1-G5 in each direction, and A/B HS rate series

Connectivity capabilities
  • Supports testing of 1.6, 1.61, 1.8, and 2.0 connection compatibility

PHY testing
  • Complete support of test mode

Test feature
  • Supports complete test feature functionality

CDR
  • Supports clock data recovery

PAM4
  • Supports PAM4 signaling mechanism

HS-G6 with 1b1b Encoding
  • Supports HS-G6 data rate with 1b1b encoding

TFS
  • Supports newly added frame structure as per UniPro 3.0

Pre-Coding and Gray Coding
  • Supports newly added encoding schemes for HS-G6 in UniPro 3.0

TFS Error Handling
  • Supports error FEC (detection and correction) for TFS frames as per UniPro 3.0

Link Equalization Training
  • Supports Link Equalization to identify the optimal values of Tx Equalization settings

Block Diagram

Simulation VIP for MIPI UniPro block diagram

Benefits

  • Compliance: Contains predefined checks to verify that the DUT agents adhere to the protocol rules
  • Error detection: Supports error detection on all layers, more than 240 different protocol checks
  • Coverage: Monitors, checks, and collects coverage on bus traffic using hundreds of automatic protocol checks, including configuration and runtime checks
  • Error injection: Random and predefined error injections promote easy testing of scenarios and scenario creations
  • Environment setup: Configurable environment layers allow for early and specified verification of Data Link Layer
  • Traffic: Generates UniPro traffic on both transaction classes for host and device. Supports constrained-random bus traffic generation
  • Packet tracker creation for easy debugging
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Dynamic activation to enable setting the VIP as active/passive during run time

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for MIPI UniPro
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

Learn more about UniPro IP core

Frequently asked questions about UniPro IP cores

What is Simulation VIP for MIPI UniPro?

Simulation VIP for MIPI UniPro is a UniPro IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this UniPro?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UniPro IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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