MIPI UniPro IIP

MIPI UNIPRO compatible with MIPI UNIPRO version 1.8 and 2.0 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI UNIPRO IIP is proven in FPGA environment. The host interface of the MIPI UNIPRO can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol.

MIPI UniPro IIP is supported natively in Verilog and VHDL

• Compliant with MIPI UNIPRO specification version 1.6,1.8 and 2.0
• Supports MIPI M-PHY specification 3.0 ,4.1 and 5.0
• Supports multiple connections in L4 Layer and L4 segments
• Supports M-PHY HS data rates HS-Gear1 – Gear5, both A/B modes and PWM
• data rates PWM-G1 to PWM-G7. In Unipro 2.0 and MPHY 5.0, supports PWM-G1 gear.
• Supports CPort arbitration at both segment level and packet level
• Supports L2 data frames and control frames
• Supports up to two M-PHY lanes for UFS application
• Supports M-PHY RMMI (10,20,40 and 80) Interface in PHY layer
• Supports all power modes for M-PHY in PHY layer
• Supports all types of lane mapping (Lane 0 mapped to 1 etc)
• Supports link startup as per specs.
• Supports maximum of 32 C-Ports
• Employs round robin arbitration across C-Ports
• Supports group acknowledgement of maximum 16 frames per traffic class
• Supports retransmission of frames
• Configurable buffer spaces
• Supports CSD, CSV
• Supports UniPro test feature
• TMPI support
• Supports CPort buffer based E2E checking
• Supports Scrambling as per specs
• Supports complete DME functionality
• Supports interrupt handling for the status of data transfer and error detection in the various layers of Unipro
• Supports below latest 2.0 Version features:
• - In Unipro 2.0 version, Linkstartup sequence start either HS Mode(HS G1A or HS G1B) or LS mode(PWM G1)
• - Supports PA capability user data in PACP CAP IND frame
• - Supports L2 buffer extension
• - Supports Extended save time
• - Supports HS-G5 Gear in HS Mode
• - Supports RMMI bus width extended to 80bits per lane interface in PHY Layer
• Supports PHY layer features:
• - Transmission and reception of encoded PHY symbols.
• - Transmission of PHY IDLE symbols when no data is supplied.
• - Detection of PHY IDLE symbols.
• - Method to re-initialize the forward Link to overcome error situations.
• - Provision of different power modes and a method to signal them from transmitter to receiver.
• Supports PHY adapter layer features:
• - Transmission and reception of Data Link layer control symbols and data symbols via underlying PHY
• - Lane distribution and merging in multi-lane ports
• - Provision of MIPI UniPro power management operating modes
• - Re-Initialization of the PHY TX path
• - Transmit lane connect/disconnect features
• - One lane mapping to different lanes
• Supports Data Link layer features:
• - Frame composition and frame decomposition
• - Buffering Mechanism
• - Frame preemption
• - Triggering of PHY initialization
• - Two traffic classes by priority-based arbitration
• - Detect various protocol errors
• Supports Network layer features:
• - Packet composition and packet decomposition
• - Packet format recognition
• - Traffic Class
• - Error handling
• Supports Transport layer features:
• - Segmentation and Reassembly
• - Segment Composition and segment decomposition
• - Segment format recognition
• - Connections management
• - End-to-End flow-control
• - Error handling
• - Different CPort arbitration algorithms supported

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The MIPI UNIPRO interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases.
• Lint, CDC, Synthesis and Simulation Scripts with waiver files.
• IP-XACT RDL generated address map.
• Firmware code and Linux driver package.
• Documentation contains User's Guide and Release notes.