Overview
The TEMAC core is ideally suited for the development of high density Gigabit Ethernet communications and storage equipment.
The Xilinx Tri-Mode Ethernet MAC core is a parameterizable core ideally suited for use in networking equipment such as switches and routers. The customizable TEMAC core enables system designers to implement a broad range of integrated Ethernet designs, from low cost 10/100/1000 Mbps Ethernet to higher performance 2.5 Gigabit ports. The TEMAC core is designed to the IEEE 802.3 specification and operates in 2500 Mbps, 1000Mbps, 100 Mbps, and 10 Mbps modes. In 1000/2500Mbps mode, the TEMAC connects to the Xilinx 1/G2.5G PCS/PMA. In 1000 Mbps mode, the TEMAC core can also connect with industry standard PHY devices. In 10/100 Mbps mode, the TEMAC uses the MII interface. The Xilinx Tri-Mode Ethernet MAC, combined with the Ethernet 1G/2.5G PCS/PMA or SGMII core, provides a complete and highly flexible solution for the implementation of Ethernet Link and Physical layers and is available as a single IP through AXI 1G/2.5G Ethernet. The TEMAC core is delivered through Vivado Design Suite and is part of the comprehensive suite of Xilinx Ethernet solutions.
Learn more about Ethernet IP core
Rambus, having successfully served the data center, enterprise and infrastructure markets with line rate MACsec and IPsec products (Secure Networking), adds two new solutions for securing UET transport protocol with TSS.
Ultra Accelerator Link (UA Link) standard has been specified to enable the creation of systems comprised of multiple nodes targeting AI applications.
As factories, process plants, and robotics platforms become increasingly intelligent and interconnected, the demand for stable, low-latency data links has pushed Ethernet deeper into embedded systems. However, since designing Ethernet connectivity into industrial chips comes with its technical and logistical hurdles, engineers may face challenges when implementing Ethernet in industrial designs.
Ultra Ethernet, designed for scale out architectures, is an open, interoperable, high-performance protocol solution tailored for AI, supported by industry leaders across switch, networking, semiconductor, and system providers, as well as hyperscalers.
At the recent ECOC 2025 conference in Copenhagen, Cadence showcased its key role in enabling the future of AI infrastructure with live silicon demonstrations of several essential IP technologies for emerging 800G and 1.6T networks. Powered by Cadence's 224G SerDes IP, Cadence's Ultra Accelerator Link (UALink 1.0) scale-up and Ultra Ethernet scale-out networking solutions deliver the performance, flexibility, and interoperability needed for next-generation AI factories and hyperscale data centers.
As artificial intelligence and high-performance computing (AI/HPC) reshape industries, the need for robust, scalable, and secure connectivity has never been greater. Built from tightly integrated CPUs, GPUs, and SmartNICs, today’s compute clusters demand high-throughput, low-latency networks that can scale from die-to-die to multi-rack deployments.