Super Speed USB 3.0 Extensible Host Controller xHCI

USB3.0 Super-Speed Host

The Super-Speed USB Host Controller is designed for flexibility, ease of use and provides ASIC/FPGA designers to implement a complete USB3.0 Host for 5 Gbps operation. The Host packet traffic can be explicitly routed and need not be broadcasted. The VUSB30xHC can be customized and optimized as a standalone host chip or integrated into ASIC for a variety of applications such as PCs, Smart phone’s, etc. The D+/D- signal pins defined by USB 2.0 are not used for Super Speed operation but are provided to allow for backward compatible operation. The design is technology independent and can be easily processed in most technologies. It can be easily bridged to any industry standard bus including the PCI, PCI Express and AMBA AHB, AXI interfaces.

Super-Speed USB3.0 Extensible Host Controller (VUSB30xHCI)

The VUSB30xHC core provides a USB functional host controller that conforms to the USB 3.0 specification for Super-Speed (5 Gbps, 480 Mbps, 12 Mbps and 1.5 Mbps) functions. The xHC Host Controller has the flexibility to support USB2.0 and USB3.0 thus eliminating the need for the companion Host Controllers. It supports USB3.0 Power Management Enhancements and also enables USB Resource Management across VMs.

The extensible Host controller utilizes a common Host Buffer to initiate an USB Bus transaction for both Super-speed and USB2.0 devices. The RAM is used all kinds of USB transfers. The Bus interface unit handles the TRB transfer data storage with the Host buffers only through Bus Master DMA data transfers.

The VUSB30xHCI provides a USB 3.0 Host PIPE and UTMI+ or ULPI Transceiver Interface to connect to a Super-Speed USB transceiver. The AMBA AHB target interface provides access to the xHC internal control/status registers for a 32-bit AMBA AHB-compatible synchronous CPU through the AHB- bus bridge. The VUSB30xHCI handles data transfers to/from the RAM (host buffers) through AHB Bus Master (DMA access) to transfer TRB data between the System Memory (Application software). The xHCI Host controller for USB3.0 utilizes the host memory based transaction schedules.

This Super-Speed host controller provides the entire USB packet of encoding / decoding and also initiating Transaction packets (TP) and Data Packets (includes Data Packet Header (DPH) and Data Packet (DP)) through command TRBs, and notifies the host software with the USB events through event TRBs. USB3.0 also supports bulk streaming and burst transfers with sequence of ordered data packets, which can also recover the error packets during transfers.

A Utility is provided for parameterizing the downstream ports of the host core to the user’s requirements.

• Complies with USB 3.0 Standard for Super Speed (5 Gbps), High Speed (480 Mbps), Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps).
• Complies with Intel xHCI specification for USB (revision 0.9).
• 32-bit and 64-bit addressing capability.
• Backward compatible with USB2.0 Devices and the type A connectors.
• Eliminates the need for companion host controllers along with its associated host software.
• Supports Bulk Streaming protocol and Data bursting.
• Supports Super speed USB PIPE and UTMI+ or ULPI transceiver interface.
• Supports USB3.0 Hub with simultaneous USB3.0 and 2.0 device transfers through the same hub. Also supports USB2.0 ping and USB2.0 Hub split transactions.
• Synchronous dual port scalable 2K RAM buffer separately for IN and OUT transfers.
• Compatible USB transfer support for Control, Bulk, Interrupt and Isochronous transfers using USB3.0 Transaction / Handshake Packets and the Data Packets.
• Technology and Process independent.
• Built-in 32-bit synchronous AMBA AHB-compatible CPU interface
• Integrated Root Hub and expandable downstream ports with support for all the USB bus speeds.
• Supports USB3.0 Power Management enhancements with suspend and resume.
• Fully synthesizable
• Utility for generation of ports expandability for the Host’s downstream port.

• Verilog source code and test-bench
• scripts for simulation and synthesis