Vendor:
SmartDV Technologies
Category:
SPI / QSPI XSPI
eSPI Synthesizable Transactor
eSPI Synthesizable Transactor provides a smart way to verify the eSPI component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
eSPI Synthesizable Transactor provides a smart way to verify the eSPI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's eSPI Synthesizable Transactor is fully compliant with standard eSPI base Specification rev.1.0 and provides the following features.
Key features
- Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
- Supports addendum 0.7
- Supports Master and Slave Modes
- Supports Single, Dual and Quad modes
- Supports TX and RX operation as per specs
- Supports below transaction phases
- Command Phase
- Turn-Around Phase
- Response Phase
- Supports baud rate selection
- Supports Slave triggered transaction
- Supports Interrupts and Alert
- Supports In-band reset
- Supports below multiple channels
- Peripheral channel
- Virtual Wires channel
- Flash Access channel
- Out Of Band message channel
- Various kind of Master and Slave errors detection and handling
- Supports CRC checking
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
Block Diagram
eSPI (Enhanced Serial Peripheral Interface) Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the eSPI testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
eSPI (Enhanced Serial Peripheral Interface) Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about SPI / QSPI / xSPI IP cores
What is eSPI Synthesizable Transactor?
eSPI Synthesizable Transactor is a SPI / QSPI XSPI IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.