Vendor: Cadence Design Systems, Inc. Category: Protocol Bridge

Simulation VIP for AMBA AHB

Cadence provides a mature and comprehensive Verification IP (VIP) for the AHB specification which is part of the Arm® AMBA® famil…

Contact Provider Request Datasheet

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the AHB specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for AHB provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides an integrated solution for interconnect verification that verifies the correctness and completeness of data as it passes through the system and performance analysis that provides automated generation of testbenches. It also provides a ready-to-use Test Suite that is composed of semi-directed tests with a limited level of randomness. The VIP for AMBA AHB is it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification and is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specification: AMBA AHB v2.0, AMBA 3 AHB-Lite Protocol v1.0, AMBA 5 AHB5 update, and Armv6 AMBA Extensions

Key features

  • Multiple Agents
    • Can support any number of agents
  • Data and Address Widths
    • Supports all legal data and address widths
  • Automatic subordinate Responses
    • Configurable option to use automatic subordinate responses
  • Delay Control
    • Support to set the delay between the items on the channels
  • Manager Signals Control
    • Support for control over the values of burst signals in the read and write address channel and over the values of transfer signals in the write data channel
  • Memory Monitoring
    • Memory can be set using backdoor access
  • Subordinate Response Control
    • Support for control over the signals in the read data channel
  • Subordinate Memory Emulation
    • Data consistency check for subordinates using memories
  • Transaction Types
    • Supports monitoring and driving of all read and write transactions
  • Hunalign and Hstrb
    • Support for Hunalign and Hstrb signals. To handle unaligned accesses and mixed-endian accesses, enables the use of byte lane strobes to indicate which byte lanes are active in a transfer
  • Subordinate Responses
    • Supports all Subordinate Responses - OKAY, ERROR, SPLIT, RETRY, and XFAIL (XFAIL is relevant only for ARMv6 AMBA Extensions)
  • Lite Cortex-M3
    • Support retraction as defined in the Arm Cortex® -M3 spec
  • AHB-Lite
    • Support for Secure Transfers, Exclusive Transfers, Extended Memory Types, Multiple Subordinate Select, User Signaling, and Single-Copy Atomicity features introduced in AMBA5 AHB
  • Exclusive Accesses
    • Support for exclusive access (Armv6 AMBA extension)
  • Level 2 Cache
    • Level 2 Cache Support (Armv6 AMBA extension)

Block Diagram

Simulation VIP for AMBA AHB block diagram

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for AMBA AHB
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

Learn more about Protocol Bridge IP core

A comparison of Network-on-Chip and Busses

This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures

IP Core for an H.264 Decoder SoC

This paper presents the development of an IP core for an H.264 decoder. This state-of-the-art video compression standard contributes to reduce the huge demand for bandwidth and storage of multimedia applications. The IP is CoreConnect compliant and implements the modules with high performance constraints.

Frequently asked questions about Protocol Bridge IP cores

What is Simulation VIP for AMBA AHB?

Simulation VIP for AMBA AHB is a Protocol Bridge IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP