Vendor: SmartDV Technologies Category: CXL

OpenCAPI Synthesizable Transactor

The OpenCAPI Synthesizable Transactor is compliant with OpenCAPI TL V3.0, V3.1 and V4.0, OpenCAPI DL V1.0 and V1.5 Specifications…

Contact Provider Request Datasheet

Overview

The OpenCAPI Synthesizable Transactor is compliant with OpenCAPI TL V3.0, V3.1 and V4.0, OpenCAPI DL V1.0 and V1.5 Specifications and verifies OpenCAPI interfaces. OpenCAPI is build on top of it to make it robust. OpenCAPI Synthesizable Transactor provides a smart way to verify the OpenCAPI component of a SOC or a ASIC in Emulator or FPGA platform. OpenCAPI Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Key features

  • Compliant with OpenCAPI Transport layer Specification versions 3.0, 3.1 and 4.0.
  • Compliant with OpenCAPI Data-link layer Specification versions 1.0 and 1.5.
  • Complete OpenCAPI Tx/Rx functionality.
  • Supports the Data Link Layer and Transaction Layer of OpenCAPI Specification.
  • Supports the following Data-rates/speed
    • 19.2 Gbps
    • 20.0 Gbps
    • 21.33 Gbps
    • 25.78125 Gbps
    • 25.6 Gbps
    • 31.875 Gbps
  • Supports PHY initialization.
  • Supports DL training sets.
  • Supports Lane reversal
    • X8 or X4 Degraded Lane reversal
    • X4 (when X4 is running on 8 lanes)
  • Supports Degraded modes
    • Odd lanes trained
    • Even lanes trained
    • Inside lanes trained
    • Outside lanes trained
    • Lane 1 trained
    • Lane 0 trained
  • Supports Deskew markers.
  • Supports Endpoint link speed discovery.
  • Supports Virtualisation.
  • Supports AFU packets.
  • Supports DLX packets.
  • Supports DL packets.
  • Supports Command ordering.
  • Supports Translation ordering.
  • Supports Write fragmentation 64, 128, 256 byte write operations
    • Partial write operations
    • 64, 128, 256 byte write operations
  • Supports scrambler as in OpenCAPI specification.
  • Scrambler can be enabled or disabled.
  • Supports insertion of scrambler errors.
  • Supports 64B/66B line encoding and decoding.
  • Detects and reports the following errors
    • Scrambler errors
    • Under and oversize frame
    • CRC errors
    • Framing errors
    • ACK errors
    • Encoding/Decoding errors
    • Training pattern errors
  • Supports constraints Randomization.
  • Status counters for various events on bus.
  • Supports bus accurate timing and timing checks.
  • OpenCAPI Verification IP comes with complete test suite to test every feature of OpenCAPI specification.

Block Diagram

OpenCAPI Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the OpenCAPI testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
OpenCAPI Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about CXL IP core

Industry 1st CXL 4.0 Verification IP: Transforming AI and HPC Systems

Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.

Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification

Compute Express Link (CXL) is revolutionizing data center architecture, with power management emerging as a key area of innovation. Among its power-saving mechanisms, the L0p (Low Power) state plays a pivotal role in reducing energy consumption during periods of low link activity.

Demystifying CXL Memory Interleaving and HDM Decoder Configuration

Memory interleaving is a technique that distributes memory addresses across multiple memory devices or channels. Instead of storing data sequentially in one device, the system alternates between devices at a fixed granularity. It could help improve bandwidth, reduce latency, and enhance scalability. In the context of Compute Express Link (CXL), memory interleaving is facilitated by the HDM (Host-Managed Device Memory) Decoder.

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter path forward. Cadence's blog, "Boosting AI Performance with CXL," outlines how CXL enables dynamic memory expansion, memory sharing, and maintains coherency across devices to eliminate bottlenecks and boost performance for processing training and inference in large-scale AI systems.

Frequently asked questions about CXL IP cores

What is OpenCAPI Synthesizable Transactor?

OpenCAPI Synthesizable Transactor is a CXL IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this CXL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP