Vendor: SmartDV Technologies Category: MIPI

MIPI TWP Synthesizable Transactor

MIPI TWP Synthesizable Transactor provides a smart way to verify the MIPI TWP component of a SOC or a ASIC in Emulator or FPGA pl…

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Overview

MIPI TWP Synthesizable Transactor provides a smart way to verify the MIPI TWP component of a SOC or a ASIC in Emulator or FPGA platform. MIPI TWP Synthesizable Transactor provides an smart way to verify the MIPI TWP bi-directional two-wire bus. The SmartDV's MIPI TWP Synthesizable Transactor is fully compliant with Specification for TWP version 1.0 and provides the following features.

Key features

  • Compliant with MIPI TWP version 2.0 specification.
  • Full MIPI Debug functionality.
  • Supports all Debug CCC's and Opcodes
  • Supports following three layer
  • Layer T1: Flow Control. Supported by the TWP Padding Packet.
  • Layer T2: Alignment Synchronization. Supported by the TWP Frame Synchronization Packet.
  • Layer T3: Data. Supported by the TWP Frame
  • Allows up to 111 source trace streams to be represented as a single stream and later separated by either hardware or software.
  • Supports Error handling and flushing mechanism
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Supports on-the-fly protocol and data checking
  • Ability to transmit strings to help verification of SOC
  • Notifies the test bench of significant events such as transactions, warnings, and protocol violations
  • MIPI TWP Synthesizable VIP comes with complete test suite to verify each and every feature of MIPI TWP specification
  • Status counters for various events in bus

Block Diagram

MIPI TWP Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the MIPI TWP testcases
  • Examples showing how to connect various components, and usage of Synthesiable VIP
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
MIPI TWP Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about MIPI IP cores

What is MIPI TWP Synthesizable Transactor?

MIPI TWP Synthesizable Transactor is a MIPI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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