Vendor: Cadence Design Systems, Inc. Category: MIPI

Simulation VIP for MIPI CSI-2

Cadence's best-in-class Verification IP (VIP) for MIPI® CSI-2sm for IP, SoCs and, system-level design testing.

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Overview

Cadence's best-in-class Verification IP (VIP) for MIPI® CSI-2sm for IP, SoCs and, system-level design testing.

In production since 2008 on dozens of production designs.

Cadence provides a mature and comprehensive VIP for the CSI-2 protocol, which is part of the MIPI family. Incorporating the latest protocol updates, the Cadence® VIP for CSI-2 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CSI-2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: MIPI CSI2 v1.3, v2.0, v2.1, v3.0, v4.0, MIPI D-PHY v1.2, v2.1, v2.5, MIPI C-PHY v1.0, v1.2, v2.0, MIPI CSE v1.0, MIPI PAL/CSI2 v1.0, and MIPI A-PHY v1.0.

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

PHY Interfaces
  • Supports D-PHY v2.5, C-PHY v2.0 and A-PHY v1.0 with both PHY interfaces: Serial (Dpdn/ABC/Uplink/downlink) and Parallel (PPI/APPI)

PPI Data Bus Width
  • Supports 16- and 32-bit PPI data bus width over C-PHYsm
  • Supports 8-, 16-, and 32-bit PPI data bus width over D-PHYsm
  • Supports 16-, 32-, and 64-bit APPI data bus width over A-PHYsm

Data Lanes
  • Supports one to eight PHY data lanes for DPHY and CPHY

Data Types
  • RGB → RGB444, RGB555, RGB565, RGB666, RGB888
  • RAW → RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, RAW20, RAW24, RAW28
  • YUV → YUV420 8/10-bit, legacy YUV420 8-bit, YUV420 8-bit CSPS, YUV420 10-bit CSPS
  • Generic Long Packet Data Types 1 to 4, user-defined format 1 to 8, Blanking Data, Null Packet, and Embedded Data
  • FS-FE, LS-LE, and all Generic Short Packet Codes (1 to 8)

Clock
  • Supports continuous and non-continuous TxWordClkHS and RxWordClkHS clock operation

Interleaving
  • Supports virtual channel and data type interleaving

Virtual Channel Extension
  • Supports up to 32 virtual channels over C-PHY and 16 virtual channels over D-PHY

Ultra-Low Power Mode (ULPM)
  • Supports Ultra-Low-Power mode (ULPM) on clock and data lanes

Triggers
  • Supports all 4 trigger commands, including low-power data after trigger transmission and low-power data pause

Pixel Layer
  • Supports pixel layer for RGB, RAW, and YUV422 data types
  • Supports pixel-to-byte packing

Scrambling
  • Supports lane-based data payload scrambling
  • Supports LFSR initialization for both D-PHY and C-PHY
  • Supports multiple sync word types insertion for C-PHY scrambling LFSR initialization

Latency Reduction Transport Efficiency (LRTE)
  • Supports merging multiple packets from the same frame in a single HS burst with protocol generated and consumed fillers and spacers over C-PHY and D-PHY

Efficient Packet Delimiter (EPD)
  • Supports PHY-generated and -consumed PDQ for both C-PHY and D-PHY
  • PDQ for D-PHY is HS-IDLE, and for C-PHY is sync words, when merging multiple packets with LRTE

Alternate Calibration Sequence for D-PHY
  • Supports PRBS9 generation of D-PHY Alternate Calibration Sequence includes updates of D-PHY v2.1 errata01

Frame Synchronization Packets
  • Supports increment of frame number by 1 or 2 for every FS Packet

Spacer Byte Generation
  • Supports to redefine spacers as a minimum value, as defined in the CSI2 v2.1 specification

End of Transmission packet (EoTp)
  • Supports a short packet after the last packet to indicate end of HS burst transmission

Spacers Generation
  • Supports spacers in the packet without PDQ(Packet Delimiter Quick) for CPHY and DPHY EPD option 1 and variable-length spacers for DPHY EPD option 2

Smart Region of Interest
  • Supports SEDP Packet and SROI packet option 1 and 2

Unified Serial Link
  • Supports SNS- and APP-initiated USL transactions in HS/LPDT mode and transport integrity checks
  • Supports USL BTA switch registers
  • Supports switching to soft standby and streaming mode
  • Supports Dynamic clock control

CSI-2 Over DPHY v2.5
  • ALP Mode - Support of Data transmission and all ALP control bursts
  • Fast Lane BTA - Burst Turn Around in ALP Mode
  • Clock Lane ULPS in ALP mode

CSI-2 Over CPHY v2.0
  • Fast Lane BTA - Burst Turn Around in ALP Mode

CSI2 over A-PHY v1.0
  • Supports CSI2 packet transfer over A-PHY serial and APPI interface

Camera Service Extension (CSE)
  • Supports SEP format over A/D/C-PHY

Protocol Adaptation Layer (PAL)
  • Supports all modes of TU function
  • Supports Multiple short packets in single A-Packet
CSE v2.0 FSED
  • Supports FSED Base, Security and FuSa services

Block Diagram

Simulation VIP for MIPI CSI-2 block diagram

Benefits

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection at CSI-2, D-PHY, C-PHY and A-PHY levels
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive coverage in e and SystemVerilog

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for MIPI CSI-2
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

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Frequently asked questions about MIPI IP cores

What is Simulation VIP for MIPI CSI-2?

Simulation VIP for MIPI CSI-2 is a MIPI IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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