Vendor: Cadence Design Systems, Inc. Category: MIPI

Simulation VIP for MIPI DPI

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for MIPI® DPIsm Protocols …

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Overview

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for MIPI® DPIsm Protocols provides a complete bus functional model (BFM), and integrated automatic protocol checks. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DPI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. DPI VIP is part of DSI VIP. Our VIP for DPI runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: MIPI DPI v2.0

Key features

  • Transmitter and Receiver
    • Drives or monitors all possible frames
  • Physical Layer
    • Supports all color coding (16/18/24 bits and configuration 1, 2, 3)
  • Timing Parameters
    • Supports all frame timing parameters
  • UVM Configuration
    • The user can configure the VIP agent using the UVM config class
  • Dynamic Activation Support
    • The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate

Block Diagram

Simulation VIP for MIPI DPI block diagram

Files

Product Sheet Download

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Specifications

Identity

Part Number
Simulation VIP for MIPI DPI
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

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Frequently asked questions about MIPI IP cores

What is Simulation VIP for MIPI DPI?

Simulation VIP for MIPI DPI is a MIPI IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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