Vendor: Cadence Design Systems, Inc. Category: MIPI

Simulation VIP for MIPI SPMI

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® SPMIsm (System Power Management Interface) protoc…

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Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® SPMIsm (System Power Management Interface) protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for SPMI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPMI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: MIPI specifications for SPMI v1.0 and v2.0.

Key features

  • Topology
    • Multiple subordinates and multiple mains topology
  • Clock
    • High Speed and Low Speed device classes
  • Main Connection
    • Main Connection by Detection of SSC, Bus Idle, Bus arbitration
  • Main Arbitration
    • Main Priority and Secondary arbitration requests
  • Subordinate Types
    • RCS and NRCS subordinates
  • Sl Arbitration
    • Supports A-bit and SR-bit subordinate arbitration requests
  • Packet Generation
    • Command, Address, Data, No Response Frame, SPMI commands
  • Device Address Types
    • Supports MID, GSID, USID device addresses
  • ACK/NACK
    • ACK/NACK mechanism as per version 2.0 specification
  • Arbitration Generation
    • Capability to generate simultaneous Arbitration request scenario
  • Error Injection
    • Injection/detection of errors for example parity errors/ noise spike at different arbitration level
  • SSC
    • Generation and detection of SSC (Sequence Start Condition)
  • Event Notification
    • Arbitration win/lost, error detection, command/data/address frame sent, subordinate A/SR bit eligibility status

Block Diagram

Simulation VIP for MIPI SPMI block diagram

Files

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Specifications

Identity

Part Number
Simulation VIP for MIPI SPMI
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

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Frequently asked questions about MIPI IP cores

What is Simulation VIP for MIPI SPMI?

Simulation VIP for MIPI SPMI is a MIPI IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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