Vendor: SmartDV Technologies Category: MIPI

MIPI STP Synthesizable Transactor

MIPI STP Synthesizable Transactor provides a smart way to verify the MIPI STP component of a SOC or a ASIC in Emulator or FPGA pl…

Contact Provider Request Datasheet

Overview

MIPI STP Synthesizable Transactor provides a smart way to verify the MIPI STP component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's MIPI STP Synthesizable Transactor is fully compliant with standard MIPI STP Specification and provides the following features.

Key features

  • Compliant with MIPI STP Specification version 2.0 and 2.2
  • Supports STP interface
  • Supports ATB interface
  • Supports TPIU interface
  • Supports a trace stream comprised of 4-bit frames
  • Supports for merging trace data from up to 65536 independent data sources (Masters)
  • Supports up to 65536 independent data Channels per Master
  • Supports basic trace data messages that can convey 4, 8, 16, 32, or 64 bit wide data
  • Supports Time-stamped data packets using one of several time stamp formats including
    • Gray code
    • Natural binary
    • Natural binary delta
    • Export buffer depth (legacy STPv1 timestamp that requires DTC support)
  • Supports Data packet markers to indicate packet usage by higher-level protocols
  • Supports Flag packets for marking points of interest (for higher-level protocols) in the stream
  • Supports Packets for aligning time stamps from different clock domains
  • Supports Packets for indicating to the DTC the position of a trigger event, which is typically used to control actions in the DTC
  • Supports Packets for cross-synchronization events across multiple STP sources
  • Supports for user-defined data packets
  • Facilities for synchronizing the trace stream on bit and message boundaries
  • Supports all types of error insertion and detection
    • Invalid Time-stamp format
    • Invalid opcode
    • Invalid async pattern
    • Invalid version

Block Diagram

MIPI STP Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the MIPI STP testcases
  • Examples showing how to connect and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
MIPI STP Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about MIPI IP core

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.

MIPI: Powering the Future of Connected Devices

From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.

Frequently asked questions about MIPI IP cores

What is MIPI STP Synthesizable Transactor?

MIPI STP Synthesizable Transactor is a MIPI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP