MIPI C/D-PHY Combo IP
The C/D-PHY Combo IP delivers top-tier PPA characteristics and is mass production-proven across multiple customer SoCs.
Overview
The C/D-PHY Combo IP delivers top-tier PPA characteristics and is mass production-proven across multiple customer SoCs.
It is available as a complete subsystem with Qualitas’ own CSI-2 and DSI-2 controller IPs, enabling streamlined integration for camera and display applications.
The IP can be customized to meet specific SoC requirements, providing design flexibility for diverse system needs.
Key features
- Compliant to MIPI D-PHY v3.0, C-PHY v2.1 specification
- D-PHY TX/RX : 80Mb/s ~ 9.0Gb/s
- C-PHY TX/RX : 80Ms/s ~ 8.0Gs/s
- Area efficient macro optimized for placement for dense SoC designs
- Support Uni-(TX or RX) and Bi-directional(TX and RX) mode
- Support emphasis architecture over lossy channel for TX
- Support equalize architecture over lossy channel for RX
- Controllable Bandwidth-power scaling
- Low power mode turn-on based on channel condition
- Power gating architecture reduce leakage power
- Clock gating for low-power consumption
- Support Eye open monitor
- Support internal and external loopback test
Block Diagram
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Standards & Interfaces
Provider
Learn more about MIPI PHY IP core
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Frequently asked questions about MIPI PHY IP
What is MIPI C/D-PHY Combo IP?
MIPI C/D-PHY Combo IP is a MIPI PHY IP core from Qualitas Semiconductor listed on Semi IP Hub.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.