Pulse Per Second (PPS) Clock to PPS core
NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configura…
- IEEE-1588 / PTP
- Now
Time Synchronization IP cores enable standards-based low-speed control and peripheral communication in modern SoC and ASIC designs.
These IP cores support precise time distribution and timestamp coordination across distributed embedded and networking systems, helping designers integrate interoperable control links across embedded, automotive, industrial, and connectivity-focused systems
This catalog allows you to compare Time Synchronization IP cores from leading vendors based on feature set, latency, power consumption, and process node compatibility.
Whether you are designing industrial automation, telecom infrastructure, automotive networks, or synchronized control systems, you can find the right Time Synchronization IP for your application.
Pulse Per Second (PPS) Clock to PPS core
NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configura…
Radio Clock (DCF77) Master core
NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…
Radio Clock (DCF77) Slave core
NetTimeLogic’s DCFSlave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DC…
NMEA Time of Day (ToD) Slave core
NetTimeLogic’s NMEATime Of Day (ToD) Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to …
NMEA Time of Day (ToD) Master core
NetTimeLogic’s Time Of Day (ToD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to syn…
NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an…
NetTimeLogic’s IRIG Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize othe…
Pulse Per Second Master (PPS) core
NetTimeLogic’s PPS Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…
Pulse Per Second Slave (PPS) core
NetTimeLogic’s PPS Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a P…
Time aligned Signal Timestamper core
The Signal Timestamper from NetTimeLogic is a timestamper with nanosecond resolution (second and nanosecond format).
IEEE1588 & IEEE802.1AS PTP Timestamp Unit (TSU) core
NetTimeLogic’s PTP Timestamp Unit is an implementation of a single port Frame Timestamp Unit (TSU) according to IEEE1588-2008 (PT…
IEEE1588 & IEEE802.1AS PTP Hybrid Clock (HC) core
The PTP Hybrid Clock (HC) from NetTimeLogic is a combination of NetTimeLogic's PTP Transparent Clock (TC) and PTP Ordinary Clock …
IEEE1588 & IEEE802.1AS PTP Transparent Clock (TC) core
The PTP Transparent Clock (TC) from NetTimeLogic is a fully scalable implementation of a Peer-To-Peer, One-Step Transparent Clock…
IEEE1588 & IEEE802.1AS PTP Ordinary Clock (OC) core
The PTP Ordinary Clock (OC) from NetTimeLogic is an extension to a single port of NetTimeLogic's PTP Transparent Clock (TC).
Precision Time Protocol or PTP or IEEE1588 is one such protocol that allows synchronization of an order of 1us with the master (m…
TS5(Thermal Sensor) Verification IP provides an smart way to verify the TS5 bi-directional two-wire bus.
Microsecond Channel (MSC) Verification IP
The MSC Verification IP is compliant with 2005-01-0057 specification and verifies MSC Bus interfaces.
TS5 Slave interface provides full support for the two-wire TS5 synchronous serial interface, compatible with JEDEC TS5111, TS5110…
TS5 Master interface provides full support for the two-wire TS5 synchronous serial interface, compatible with JEDEC TS5111, TS511…
IEEE 1588 core is compliant with IEEE Standard 1588-2019 specification.