Vendor: eSi-RISC Category: FPU

Half precision, IEEE 754, floating point fused multiply add

The eSi-HP-FP-Fused-Multiply-Add IP core implements half-precision (16-bit), IEEE 754 compliant, floating-point fused multiply an…

Contact Provider Request Datasheet

Overview

The eSi-HP-FP-Fused-Multiply-Add IP core implements half-precision (16-bit), IEEE 754 compliant, floating-point fused multiply and add operations.

Key features

  • Half-precision (16-bit) floating point fused multiply and add.
  • IEEE 754 compliant.
  • Full support for infinities, NaNs and denormals.
  • Rounding is to the nearest even number.
  • Status flags indicating invalid, overflow, underflow and inexact.
  • Optional pipeline registers.
  • Supports one operation per cycle.

What’s Included?

  • Verilog RTL
  • Testbench
  • Simulation and synthesis scripts
  • Documentation

Specifications

Identity

Part Number
eSi-HP-FP-Fused-Multiply-Add
Vendor
eSi-RISC
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

eSi-RISC
HQ: UK
eSi-RISC designs and licenses the eSi-RISC range of configurable, low-power, RISC CPU IP cores, as well as associated peripheral IP cores and software development tools. The eSi-RISC processors are unique in being configurable from a base 16-bit core (eSi-1600) to a 32-bit, multi-core CPU with optional caches (eSi-3250), to a high-performance DSP core with 64-bit fixed-point SIMD and floating point support (eSi-3264). As well as supplying individual cores, eSi-RISC can develop complete SoC sub-systems combining CPUs, memory and peripherals (DMA, memory-controllers, I2C, UART, SPI, etc.), using an AMBA AXI/AHB/APB based interconnect, generated automatically using our eSi-SoC EDA tool.
Contact eSi-RISC

Learn more about FPU IP core

A formal-based approach for efficient RISC-V processor verification

In this article, we go through a formal-based, easy-to-deploy RISC-V processor verification application. We show how, together with a RISC-V ISA golden model and RISC-V compliance automatically generated checks, we can efficiently target bugs that would be out of reach for simulation.

Efficient Verification of RISC-V processors

Processor verification, however, is never trivial but requires combining the strengths of multiple verification techniques. This technical paper considers how to efficiently verify a RISC-V processor using a multi-layered approach known as the Swiss cheese model adapted from the world of avionics.

Frequently asked questions about FPU IP cores

What is Half precision, IEEE 754, floating point fused multiply add?

Half precision, IEEE 754, floating point fused multiply add is a FPU IP core from eSi-RISC listed on Semi IP Hub.

How should engineers evaluate this FPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP