FPU IP cores accelerate floating-point computation for numerically demanding workloads in modern SoC and ASIC designs.
These IP cores implement IEEE-style floating-point operations to improve performance for control, graphics, scientific, DSP, and AI-related tasks that benefit from dynamic range
This catalog allows you to compare FPU IP cores from leading vendors based on floating-point throughput, latency, precision support, and process node compatibility.
Whether you are designing embedded processors, DSP systems, scientific compute blocks, or graphics and control applications, you can find the right FPU IP for your application.
Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
This circuit uses Altera’s new Arria and Stratix 10 FPGAs with hardwired support for floating-point operations (IEEE754).
Single precision floating-point 2 cycle's multiplier
Fastest multiplier only two cycles .
Single precision floating-point fast speed parametrized multi operands adder
Single precision floating-point fast speed parametrized multi operands adder.
The FPU Verification IP provides an effective & efficient way to verify the components interfacing with FPU interface with a RISC…
Half precision, IEEE 754, floating point fused multiply add
The eSi-HP-FP-Fused-Multiply-Add IP core implements half-precision (16-bit), IEEE 754 compliant, floating-point fused multiply an…
Single precision, IEEE 754, integer to floating point conversion
The eSi-SP-FP-Int-to-Float IP core implements single-precision (32-bit), IEEE 754 compliant, integer to floating-point conversion.
Single precision, IEEE 754, floating point to integer conversion
The eSi-SP-FP-Float-to-Int IP core implements single-precision (32-bit), IEEE 754 floating-point to integer conversion.
Single precision, IEEE 754, floating point square root
The eSi-SP-FP-Square-Root IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point square root operations.
Single precision, IEEE 754, floating point divider
The eSi-SP-FP-Divider IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point division.
Single precision, IEEE 754, floating point multiplier
The eSi-SP-FP-Multiplier IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point multiplication.
Single precision, IEEE 754, floating point adder
The eSi-SP-FP-Adder IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point addition and subtraction ope…
Library of mathematical and floating point (FP) components
Optimized for efficient hardware implementation, the Synopsys Foundation Cores include a library of mathematical and floating poi…
Half Precision IEEE-754R complete FPU for graphics processing
The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for…
Double & Single Precision IEEE-754 complete FPU
The A2FD is a fully synthesizable module implemented in Verilog RTL.
Very high performance IEEE-754 modules
The A2FM product is a collection of floating-point execution units compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for B…
Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
The extended dynamic range and precision offered by floating-point arithmetic is quickly becoming a requirement in numerous signa…
Single Precision IEEE-754 complete FPU
The A2F is a fully synthesizable module implemented in Verilog RTL.
Vector Floating-point coprocessor based on ARM VFPv2 Instruction Set Architecture for FA626TE 32-bit RISC CPU