Vendor: Synopsys, Inc. Category: FPU

Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors

The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…

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Overview

The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where high-performance and high clock speed are required. The processors can be clocked at up to 1.8 GHz in 16FFC processes (worst case, single core, base configuration) and offer outstanding performance delivering 3.0 DMIPS/MHz and 6.16 CoreMark/MHz with a small area footprint and low power consumption.

The ARC HS66 and HS68 processors are based on the advanced ARCv3 instruction set architecture (ISA) and pipeline, which provides leadership power efficiency and code density. The processors feature a 52-bit physical address space and can directly address memories up to 4.5 Petabytes(4.5x1015) in size. For applications requiring higher performance, Multicore Processor (MP) versions of the HS66 and HS68 are available with support for up to 12 HS CPU cores and up to 16 hardware accelerators in the processor cluster.

The ARC HS66 features level 1 (L1) instruction and data cache and closely coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications. The HS68 is designed for use in applications running Linux or SMP Linux. The HS68 has all the features of the HS66 plus support for L2 cache up to 64 MB and a Memory Management Unit (MMU).

To maximize PPA of ARC HS6x-based processor designs, a Fusion QuickStart Implementation Kit (QIK) that includes tool scripts, a baseline floorplan, design constraints and documentation, is available.

Key features

  • Dual-issue, 64-bit processors for high-performance embedded applications
  • 52-bit physical and 64-bit virtual addressing
  • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
  • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
  • Based on advanced ARCv3 ISA
  • High degree of configurability
  • Enhanced MMU (HS68) with hardware page table walk and up to 16 MB page sizes
  • Support for custom instructions
  • Support for up to 16 MB of closely coupled memory and direct mapping of peripherals
  • Floating Point Unit (FPU) supporting half, single- and double-precision IEEE 754-compliant operation
  • ARC Trace Interface provides real-time trace debugging features
  • Fusion QuickStart Implementation Kit (QIK) with tool scripts, a baseline floorplan, design constraints and documentation maximizes PPA
  • Easy performance upgrade from HS3x and HS4x processors

Block Diagram

dwc_arcv3_hs_fpu_option block diagram

Specifications

Identity

Part Number
dwc_arcv3_hs_fpu_option
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

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Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Contact Synopsys, Inc.

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Frequently asked questions about FPU IP cores

What is Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors?

Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors is a FPU IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this FPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FPU IP.

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