General Purpose PMU - Thermal shutdown and overvoltage protected - SilTerra 0.18 um
This macro-cell is a Power Management Unit (PMU) core designed for Silterra 0.18µm C18GH5 CMOS technology in TO (thick oxide) and…
Overview
This macro-cell is a Power Management Unit (PMU) core designed for Silterra 0.18µm C18GH5 CMOS technology in TO (thick oxide) and HP (thin oxide) process.
The circuit has two linear voltage regulators (one of which has an external feedback connection), internal voltage and bias current generators, built-in poweron-reset (POR), thermal shutdown and overvoltage protection. An internal voltage reference provides a range of voltages for the sake of flexibility of the IP.
The core is easily retargeted to any other CMOS technology with R-poly devices.
Key features
- Regulated 1.8V output voltage with overvoltage protection
- Regulated 2.7V output voltage
- Bandgap reference = 1.2V
- Built-in current reference and POR
- Thermal shutdown
Block Diagram
Applications
- Battery Chargers
What’s Included?
- Datasheet/Integration Guide
- HDL Model
- Flat GDSII database/LVS netlist
- Customer Support
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| Silterra | 180nm | G | Silicon Proven |
Specifications
Identity
Provider
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Semiconductor IP FAQ
What is General Purpose PMU - Thermal shutdown and overvoltage protected - SilTerra 0.18 um?
General Purpose PMU - Thermal shutdown and overvoltage protected - SilTerra 0.18 um is a Power Management Unit IP core from Chipus Microelectronics listed on Semi IP Hub. It is listed with support for silterra Silicon Proven.
How should engineers evaluate this Power Management Unit?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power Management Unit IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.