1.2V SLVS Transceiver in UMC 110nm
A 200Mbps 1.2V SLVS transceiver solution.
- UMC
- 110nm
Foundation Libraries IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Foundation Library IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
1.2V SLVS Transceiver in UMC 110nm
A 200Mbps 1.2V SLVS transceiver solution.
U40LPGPIOLEDV1 is a general purpose I/O with LED driving IP.
Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)
The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrate…
The HSTL library includes the driver / receiver cells and a full complement of power and support cells for both single-ended and …
The SSTL_2 pad set is a full complement of I/O, power, and spacer cells (total of 14 cells) that are necessary to assemble a padr…
UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming
UMC 65nm SP/RVT Logic Process MPCA cell library
UMC 65nm SP/RVT Logic Process MPCA cell library
UMC 90nm LL/RVT MPCA core cell library
UMC 90nm LL/RVT MPCA core cell library
UMC 0.18um Generic process MPCA core cell library
UMC 0.18um Generic process MPCA core cell library
UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)
UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)
UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)
UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)
UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)
UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60).
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library
UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library