Vendor: Comcores Category: Single-Protocol PHY

Ethernet PCS 10G/25G

Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…

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Overview

Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018

The Ethernet PCS 10G/25G IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 and with Clause 49 of IEEE 802.3ae specification.

The Ethernet PCS 10G/25G IP supports 10G and 25G line rates, however other Ethernet PCS speeds are available, such as 1G/2.5G and 100G.

On one side it interfaces to a SerDes device and on the application side it has a port for GMII/SGMII Ethernet signals.

The Ethernet PCS 10G/25G IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.

Key features

Delivers Performance

  • Designed to IEEE 802.3-2018
  • Supports Ethernet speeds of 10G and 25G
  • Complete 10GBASE-R and 25GBASE-R PCS solution
  • Can be used in any 10G or 25G Ethernet PHY application

Feature Rich

  • Configurable for several operating modes and speeds
  • Works with multiple SerDes widths
  • IEEE Std. 802.3 Clause 46 Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII)
  • IEEE Std. 802.3 Clause 49 Physical Coding Sublayer (PCS) for 64B 66B, type 10GBASE-R
  • IEEE Std. 802.3 Clause 107 Physical Coding Sublayer (PCS) for 66B 66B, type 25GBASE-R
  • IEEE Std. 802.3 Clause 45 Management Data Input/Output (MDIO) Interface
  • IEEE Std. 802.3 Clause 74 Forward Error Correction (FEC) sublayer for BASE-R PHYs
  • IEEE Std. 802.3 Clause 78 Energy-Efficient Ethernet (EEE)
  • IEEE Std. 802.3 Clause 108 Reed-Solomon Forward Error Correction
  • (RS-FEC) sublayer for 25GBASE-R PHYs
  • Support XGMII for 10G and XXVGMII for 25G
  • PMA/SerDes interface is default 40-bit, with 32, 64 and 66 bit being optional
  • 64B 66B encoding/decoding

Highly Configurable

  • Enabling the use of multiple rates of Ethernet
  • Easy interfacing to standard MAC’s
  • Several common control bus standards are supported
  • Can be delivered with an integrated MAC for plug and play
  • Includes test pattern Generator/Checker

Silicon Agnostic

  • Designed in SystemVerilog and targeting both ASICs and FPGAs

Block Diagram

Ethernet PCS 10G/25G block diagram

What’s Included?

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note
  • Simulation Environment, including Simple Testbed, Test case and Test Script
  • Programming Register Specification
  • Timing Constraints in Synopsys SDC format
  • Access to support system and direct support from Comcores Engineers
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Ethernet PCS 10G/25G
Vendor
Comcores

Provider

Comcores
HQ: Denmark
Comcores is a market leader in the development of state-of-the-art IP-cores for communication systems. The company is a leading provider of digital components for high-speed digital connectivity between wireless communication network components as well as radio functionality in existing and next-generation mobile infrastructure networks. Comcores offers leading IP cores solutions, expertise in research and development as well as custom design solutions.
Contact Comcores

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Frequently asked questions about Single-Protocol PHY IP

What is Ethernet PCS 10G/25G?

Ethernet PCS 10G/25G is a Single-Protocol PHY IP core from Comcores listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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