Learn more about Ethernet IP core
Rambus, having successfully served the data center, enterprise and infrastructure markets with line rate MACsec and IPsec products (Secure Networking), adds two new solutions for securing UET transport protocol with TSS.
Ultra Accelerator Link (UA Link) standard has been specified to enable the creation of systems comprised of multiple nodes targeting AI applications.
As factories, process plants, and robotics platforms become increasingly intelligent and interconnected, the demand for stable, low-latency data links has pushed Ethernet deeper into embedded systems. However, since designing Ethernet connectivity into industrial chips comes with its technical and logistical hurdles, engineers may face challenges when implementing Ethernet in industrial designs.
Ultra Ethernet, designed for scale out architectures, is an open, interoperable, high-performance protocol solution tailored for AI, supported by industry leaders across switch, networking, semiconductor, and system providers, as well as hyperscalers.
At the recent ECOC 2025 conference in Copenhagen, Cadence showcased its key role in enabling the future of AI infrastructure with live silicon demonstrations of several essential IP technologies for emerging 800G and 1.6T networks. Powered by Cadence's 224G SerDes IP, Cadence's Ultra Accelerator Link (UALink 1.0) scale-up and Ultra Ethernet scale-out networking solutions deliver the performance, flexibility, and interoperability needed for next-generation AI factories and hyperscale data centers.
As artificial intelligence and high-performance computing (AI/HPC) reshape industries, the need for robust, scalable, and secure connectivity has never been greater. Built from tightly integrated CPUs, GPUs, and SmartNICs, today’s compute clusters demand high-throughput, low-latency networks that can scale from die-to-die to multi-rack deployments.
