How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SMIC
Category:
DDR
DDR3/DDR2/LPDDR2 COMBO Interface
Key features
- DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
- SMIC 40nm Logic Low Leakage Salicide 1.1V/1.8V/2.5V Process
- Cell Size (Width * height) 30um * 280um with DUP stagger bonding pads
- Work IO voltage: 1.2V/1.5V/1.8V
- Programmable driven-strength, programmable ODT,support DDR3-1333,DDR2-1066,LPDDR2-1066
- Suitable for 8 layer application
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 40nm | 40nm 400 nm | Silicon Proven |
Specifications
Identity
Part Number
SP40NLLD2P_MEMIO_COMBO3
Vendor
SMIC
Type
Silicon IP
Provider
SMIC
HQ:
China
Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in mainland China. SMIC provides integrated circuit (IC) foundry and technology services at 0.35-micron to 28-nanometer. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and a 200mm mega-fab in Shanghai; a 300mm mega-fab in Beijing and a majority owned 300mm fab for advance nodes under development; a 200mm fab in Tianjin; and a 200mm fab project under development in Shenzhen. SMIC also has marketing and customer service offices in the U.S., Europe, Japan, and Taiwan, and a representative office in Hong Kong.
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Frequently asked questions about DDR Interface IP
What is DDR3/DDR2/LPDDR2 COMBO Interface?
DDR3/DDR2/LPDDR2 COMBO Interface is a DDR IP core from SMIC listed on Semi IP Hub. It is listed with support for smic Silicon Proven.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.