Vendor: Eureka Technology, Inc. Category: DDR

DDR2 SDRAM Controller

DDR2 SDRAM Controller

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Key features

  • Supports industry standard Double Data Rate (DDR) and Double Date Rate2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes.
  • Issue precharge, active and read/write commands to a different banks and keeps multiple banks active at the same time.
  • Integrated data buffer (Soft PHY) captures and synchronizes SDRAM data using programmable delay cells or DLL.
  • Supports bulit-in soft DDR PHY or external hard PHY such as DFI.
  • User controlled variable additive latency for DDR2 device.
  • On-die termination (ODT) support optimized for single and multiple SDRAM DIMM.
  • Off-Chip Driver impedance adjustment (OCD) support for DDR2 devices.
  • Programmable SDRAM access timing parameters and configurations.
  • Automatic refresh generation with programmable refresh intervals.
  • Self-refresh mode to reduce system power consumption.
  • Differentiating Features
    • Multi port input.
    • Mobile DDR.
    • Multiple clock domain for user ports.
    • Multiple SoC and FPGA standard bus interface support (e.g. AHB, Avalon, PowerPC, Wishbone, SH4).

Block Diagram

EP532 block diagram

Specifications

Identity

Part Number
EP532
Vendor
Eureka Technology, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Eureka Technology, Inc.
HQ: USA
Eureka Technology Inc. provides reusable IP cores for ASIC, PLD and system designs. These system level function cores are designed to:
  • Shorten Time-to-market
  • Eliminate Design Risks
  • Reduce Development Costs
As today's technologies evolve in a very fast pace, design engineers are constantly looking for ways to speed up the design cycle in order to have product in the market ahead of the competitions. The use of reusable IP cores in IC and system design has emerged as the methodology of choice to address the needs for rapid productization, fast prototyping and software/hardware co-development. Eureka Technology help design engineers stay in the forefront of this new design methodology by providing reusable IP cores. Our reusable IP cores are silicon proven and pre-verified to meet and exceed customer requirements. Design risk is virtually eliminated since each one of these cores has been fully tested and proven in real world applications. Since founded in 1993, Eureka Technology has established itself as a leading reusable IP core provider with customer base in the United States, Japan, and Europe. We have provided reusable IP cores to many market leaders in the computer, electronics and semiconductor industries. Our technologies have been incorporated into tens of million dollars' worth of products sold by our customers. We also have entered partnership agreements with leading silicon vendors to incorporate our reusable IP cores into their silicon products. However, our important partnership is the one with our customers and we would like to be the design partner for your next project.
Contact Eureka Technology, Inc.

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is DDR2 SDRAM Controller?

DDR2 SDRAM Controller is a DDR IP core from Eureka Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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