DDR1 DDR2 SDRAM Memory Controller

Increasing SoC/ASIC devices' complexity also demands increase in memory bandwidth. Single data rate devices are being replaced by double (and more) data rate devices in applications where memory bandwidth is essential. The development trend in DDR2, DDR, SDRAM devices is biased towards higher clock frequencies and higher latencies. Beyond DDR2/DDR SDRAM Memory Controller IP Core was developed with this trend in mind. It interleaves accesses when possible, maximizing utilization of memory control and data buses. This reduces overall memory access latencies while utilizing its higher bandwidth capabilities.

Beyond DDR2/DDR SDRAM Memory Controller IP Core provides access to external synchronous dynamic memory devices for SoC designs using multiport AMBA AHB or WISHBONE Rev. B3 SoC interconnect bus as internal bus. A wide variety of different memory device organizations and speeds are supported. Beyond DDR2/DDR SDRAM Memory Controller IP Core also uses a lot of optional, compile time parameters, which makes it configurable for use in a wide variety of applications.

• Memory Interface
  • Compile time configurable number of chip select signals – two to four
  • Software programmable chip select address range for each chip select – 8MB to 4GB
  • Compile time configurable memory data bus width. Supported 16, 32 and 64 bits
  • Utilization of write data mask signals for incomplete write bursts
  • Compile time configurable memory address bus width
  • Standard DDR SDRAM control interface
  • Possible SDRAM burst sizes are 1, 4, 8 for DDR and 2, 4, 8 for SDR
  • Software programmable SDRAM memory organization
  • Additional DDR2 SDRAM control interface
  • Independent of data transmit and capture (physical layer) implementation
  • Pipelined, out-of-order memory command generation. Number of pipeline stages is selected at compile time according to application needs
  • Automatic SDRAM refresh generation
  • Register interface for software initialization and suspension of external memory devices
  • Pipelined, out-of-order memory command generation. Number of pipeline stages is selected at compile time according to application needs
  • Automatic SDRAM refresh generation
  • Register interface for software initialization and suspension of external memory devices
  • Page tracking logic implemented to reduce access latencies. Tracked number of pages is selected at compile time according to application needs
• Supported Soc Bus Interconnect
  • The core is available with support for any of the following interconnect options:
    • AMBA:
      • AHB for memory access ports
      • APB for configuration port (for setting memory timings, etc.)
    • WISHBONE Rev. B.3 compliant interfaces (efficient burst transfers supported)
      • All WISHBONE burst, classic and single transfer cycles are supported for write and read operations
    • Interface Features
      • The Memory Controller IP Core implements up to four SoC Bus interconnect interfaces (either AMBA AHB or WISHBONE)
      • SoC Bus Interconnect Interface burst operations are taken advantage of to increase memory and buses utilization
      • Each memory access port can be configured at compile time to support either 32 or 64 bit data width
      • Separate configuration port interface is used for core, external memory devices and physical layer configuration
    • Core Internals
      • The core can run memory interface at any integer multiple frequency of that at SoC Interconnect Interface
      • The core's implementation provides compile time parameters to configure control and data paths. Parameters can enable sharing of same resources for different Bus Interface ports, reducing overall application silicon area

• RTL Verilog source code
• Verilog Test bench
• Documentation
• Example implementation
• Hardware platform (optional)
• Engineering Support