How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
HCL Technologies
Category:
DDR
DDR3 Controller IP
The AXI DDR3 Controller provides access to DDR3 memory.
Overview
The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access. While doing this it combines AXI burst transactions into single DDR access where ever possible to achieve the best possible performance from DDR3 memory subsystem.
Key features
- High memory throughput achieved via Parallel operation of all the banks and reordering of commands in the controller to ensure the maximum utilization of the DDR Memory
- Pipelined operation across the complete design to ensure the highest performance
- DDR Interface
- Supports all standard DDR3 (x4,x8,x16) SDRAMs
- Supports power down modes
- Run-time configurable timing parameters and memory settings
- Automatic generation of initialization and refresh sequences
- All burst lengths (4 & 8) supported
- AXI Interface
- Supports AMBA 3 AXI protocol 32 bit Data Width
- Does re-mapping/combines the AXI Burst transactions into memory transactions by understanding the memory architecture
- Supports unaligned transactions
- Supports multiple outstanding transactions
- Supports delayed Writes(Independent AXI command and Data Channel )
What’s Included?
- Verilog RTL/Synchronous Design
- Test Plan, Test Bench ,Test Cases & Test Results
- Architecture Doc & LLD of Individual Blocks
- ISE & DC Synthesis Scripts
Specifications
Identity
Part Number
SIP_DDR3
Vendor
HCL Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HCL Technologies
HQ:
India
HCLTech is one of Indias leading global Technology and IT enterprises, operating across 61 countries and with annual revenues of US$13 billion. Our range of offerings span R&D and Technology Services, Enterprise and Applications Consulting, Remote Infrastructure Management, BPO services, IT Hardware, Systems Integration and Distribution of Technology and Telecom products in India. HCLTech specializes in spec to parts custom SoC design service. HCLTech design house is focused on designing high-performance hardware engineering solutions. Our robust processes, development methodology, expertise in complete system engineering including ASIC / FPGA (mixed signal), ESL (Electronic System Level), Board Design & Firmware have enabled our customers to improve the design cycle and achieve faster go to market. We have also provided significant value to our customers through our reusable IP cores, automated test / verification frameworks and other solution accelerators. Our expertise spans across tools from Cadence, Mentor, Synopsys and others.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
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Frequently asked questions about DDR Interface IP
What is DDR3 Controller IP?
DDR3 Controller IP is a DDR IP core from HCL Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.