How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Atria Logic, Inc.
Category:
DDR
QDR IV XP PHY + Memory Controller
Atria Logic with its vast expertise and working experience for more than a decade in memory domains, brings a high speed PHY and …
Overview
Atria Logic with its vast expertise and working experience for more than a decade in memory domains, brings a high speed PHY and Memory Controller for next generation memories introduced under the QDR consortium. Working at high speeds it garnishes the maximum speed of Stratix V FPGAs at 800MHz. De- skew training sequences, per-bit calibration and rate conversions at high speeds from uer interface (quarter rate) to memory interface (full rate) are some its features.
Key features
- Standard: QDR IV XP (Extreme Performance) PHY and Memory Controller
- Frequency: Memory Interface : 800MHz
- User Interface : 200MHz
- Write Latency at Memory Interface : 5 Full Rate Cycles
- Read Latency at Memory Interface : 8 Full Rate Cycles
- Burst Length : 2 Words
- Calibration : Per-bit calibration for data, command and address on memory interface.
- Data Modes: x18 mode supported at 2 ports respectively. At one FR cycle 2 x (18+18) = 72b of data transferred.
- FPGA Platform: Stratix V FPGA
Block Diagram
AL-QDR4-PHY-MEMCNTRL block diagram
Applications
- High performance networking and communication applications
- Servers
What’s Included?
- FPGA specific netlist
- Complete HDLtestbench
- Test images
- Data Sheet and Users Guide
Specifications
Identity
Part Number
AL-QDR4-PHY-MEMCNTRL
Vendor
Atria Logic, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Atria Logic, Inc.
HQ:
USA
Atria Logic is a leading provider of HW/SW FPGA and SoC IP cores and design engineering services, specializing in applications for medical imaging, multimedia, storage and networking. In addition, we also specialize in heterogeneous computing engineering services for computer vision applications in such applications as industrial automation, video surveillance and automotive.
Our IP core portfolio includes H.264 video encoders and decoders, H.264 players, DDR I/II/III and QDR IV Extreme Performance PHY and memory controllers, USB 2/3 controllers, PCIe Gen 1/2 PHYs, NVMe validation test suites, and Gb Ethernet MAC controllers. Our IP cores have been designed for ease of reuse and configurability to speed up SoC and FPGA implementations.
Our design services include IP customization, SoC integration, FPGA and SoC implementations, firmware development, software porting and optimization.
We are headquartered in Sunnyvale, California, USA, in the heart of Silicon Valley.
Technology Focus:
Video/Image processing
Heterogeneous Processing
High Power Computing
Computer Vision and Video Analytics
High speed memory controllers and Standard bus architectures
Network Processing
FPGA/ASIC/SoC design services
HW/SW domain consultancy and services
Business Domains
Medical Imaging
Video Surveillance
Industrial Automation
Enterprise and Datacenter Storage
Broadcast
Automotive Assisted Driver Assistance Systems
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Frequently asked questions about DDR Interface IP
What is QDR IV XP PHY + Memory Controller?
QDR IV XP PHY + Memory Controller is a DDR IP core from Atria Logic, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.