I/O Library
Dolphin Technology offers an extensive array of Interface IP, all of whichhasbeen optimized for ultra high performance across all…
Overview
Dolphin Technology offers an extensive array of Interface IP, all of whichhasbeen optimized for ultra high performance across all processes supported. Our I/O portfolio includes: Standard I/O (General Purpose I/O or GPIO), Specialty I/O (bus-specific I/O), NAND Flash I/O and DDRx & LPDDRx I/O.
Dolphin Technology offers one of the industry's largest selections of Interface IP, all of which has been optimized for ultra high performance across all processes supported. Our I/O portfolio includes:
- Standard I/O (General Purpose I/O or GPIO)
- GPIO High Voltage Tolerant
- GPIO High Voltage Capable
- GPIO High Voltage Tolerant Failsafe (for selected technologies)
- GPIO High Voltage Capable Failsafe (for selected technologies)
- Crystal Oscillator Pad
- 32KHz
- 1MHz - 50MHz
- Specialty I/O (bus-specific I/O)
- LVDS Tx/Rx
- LVDS/GPIO Combo
- DDR4/3 & LPDDR4/3 Combo
- DDR3/2 & LPDDR3/2 Combo
- eMMC I/O
- SD 2.0 I/O
- SD UHS2 I/O
- I2C I/O
- I3C I/O
- I2S I/O
- ONFI
- MDIO
- SSTL
- HSTL
- CML
- RGMII
- RC Oscillator
- Oscillator Pad pitch compatible with GPIO
- Multi Function IO
We specialize in Staggered, Inline and Flip Chip pads with aggressive pitch for the most demanding designs, whether pad or core limited. Plus, our I/O Compiler enables us to customize the entire library based on process-specific and chip-specific options.
| GENERAL PURPOSE I/O | 2/3nm | 4/5nm | 6/7nm | 12/16nm | 22/28nm | 40nm | 55nm | 65nm | 80nm | 90nm |
| I/O drive strengths 2/4/6/8/10/12 mA | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| 1.5V Xtrs, 1.8V output drive/2.5V Tolerant | 🟢 | 🟢 | ||||||||
| 1.5V Xtrs, 1.8V/2.5V output drive Capable | 🟢 | 🟢 | ||||||||
| 1.8V Xtrs, 1.8V output drive/3.3V Tolerant | 🟢 | 🟢 | ||||||||
| 1.8V Xtrs, 1.8V/3.3V output drive Capable | 🟢 | 🟢 | ||||||||
| 1.8V Xtrs, 1.8V output drive/2.5V/3.3V Tolerant | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||||
| 1.8V Xtrs, 1.8V/2.5V/3.3V output drive Capable | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||||
| 2.5V Xtrs, 2.5V output drive/3.3V Tolerant | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||||
| 2.5V Xtrs, 2.5V/3.3V output drive Capable | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| DDR I/O | 2/3nm | 4/5nm | 6/7nm | 12/16nm | 22/28nm | 40nm | 55nm | 65nm | 80nm | 90nm |
| Configurable single-ended and differential I/O's | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| DDR4/3/2 & LPDDR4/3/2 I/O with PVT Compensation and PVT compensated internal termination RTT using 1.8V Xtrs | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |||||
| DDR4/3/2 & LPDDR4/3/2 I/O with PVT Compensation and PVT compensated internal termination RTT using 2.5V Xtrs | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |||||
| DDR3/2/1 & LPDDR2/1 I/O with PVT Compensation and PVT compensated internal termination RTT using 1.8V Xtrs | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |||||
| DDR3/2/1 & LPDDR2/1 I/O with PVT Compensation and PVT compensated internal termination RTT using 2.5V Xtrs | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| NAND FLASH I/O | 2/3nm | 4/5nm | 6/7nm | 12/16nm | 22/28nm | 40nm | 55nm | 65nm | 80nm | 90nm |
| ONFI 4.2/4/3/2/1 and Toggle 2/1 NAND compliant | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| Configurable single-ended and differential I/O's | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| NAND Flash I/O with PVT Compensation and PVT compensated internal termination RTT using 1.8V Xtrs | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| Drive capability up to 80pF | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| SPECIAL PURPOSE I/O | 2/3nm | 4/5nm | 6/7nm | 12/16nm | 22/28nm | 40nm | 55nm | 65nm | 80nm | 90nm |
| LVPECL I/O with PVT Compensation | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| LVDS/LVPECL Combo with PVT Compensation | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| PCI | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| I2C/I3C | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Multi Function IO | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| I/O FEATURES | 2/3nm | 4/5nm | 6/7nm | 12/16nm | 22/28nm | 40nm | 55nm | 65nm | 80nm | 90nm |
| Libraries include configurable I/O's, power cells, fillers, spacers, and analog or calibration cells | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Pad design with 25um pitch | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Supports wirebond/CUP and flipchip packages | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Programmable metal stack options | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| 4 different slew rate options | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Built-in JTAG Logic for testability | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Input/Output registers options | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Bus-hold(sustain) and pull-up/pull-down options | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Built-in ESD and Latchup Prevention circuits | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about GPIO IP core
A Generic Solution to GPIO verification
Ensuring reliability in Advanced IC design
Integrating Post-Quantum Cryptography (PQC) on Arty-Z7
ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems
Frequently asked questions about GPIO Pad Library IP cores
What is I/O Library?
I/O Library is a GPIO IP core from Dolphin Technology listed on Semi IP Hub.
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.