Vendor: Atomic Rules LLC Category: Ethernet

UDP Offload Engine for IPv4

Atomic Rules UDP Offload Engine (UOE) is a UDP FPGA IP Core that allows for immediate operation at 10, 25, 40, 50, 100 or 400 GbE.

Overview

Atomic Rules UDP Offload Engine (UOE) is a UDP FPGA IP Core that allows for immediate operation at 10, 25, 40, 50, 100 or 400 GbE.

Interoperability with the Internet Protocol

The UDP/IP core implements the UDP/IPv4 standard RFC 768/791, including checksum, segmentation and reassembly hardware offload.

The UDP/IP core is tested for operation with popular FPGA vendors’ GbE Ethernet MACs.

Increase data transfer rates to 50/100/400 GbE without starting over

Allows for immediate operation at 10, 25 or 40 GbE, while providing a simple path to 50/100/400 GbE.

Offloads all UDP operations so you can work with datagrams

Offloads UDP standard RFC 768 from software to hardware.

L4 UDP Multicasts are pre-selected so that your application doesn’t have to perform this function

An integral IGMPv2 multicast pre-selector removes unwanted traffic.

Key features

  • Concurrent datagram send and receive
  • Ethernet packet: programmable frame MTU up to 16K Bytes (Super-Jumbo Frame support)
  • UDP packet arbitrary datagram PDU up to IPv4 limit of 64K Bytes
  • 16 Entry ARP cache (RFC 826)
  • ICMP (unsegmented echo response message type only, used by “ping”)
  • VLAN (IEEE 802.1Q) support
  • Layer 3 direct, allowing non-UDP application connectivity
  • Statistics accessible by control-plane interface
  • Low-Area implementation, allowing multiple core instances per FPGA
  • Avalon and AXI4 interfaces

Block Diagram

Benefits

  • Future proof your application; optimize throughput for all line rates
  • Operates at 10, 25, 40, 50, 100, or 400 GbE
  • Run full line rate with no packet loss, even for very small packets
  • Offloads UDP standard RFC 768 from software to hardware
  • Robust multicast support

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
UOE
Vendor
Atomic Rules LLC
Type
Silicon IP

Provider

Atomic Rules LLC
HQ: USA
We provide our clients with effective solutions to problems involving interconnection networks and reconfigurable computing. Our practice employs scalable, rule-based methods to tackle complex concurrency among heterogeneous processors. Advances in chip technology and throughput of low cost computing platforms offer significant opportunities to radically improve performance of current products. Atomic Rules understands the limitations of composing complex processor interactions using conventional RTL methods. To address this challenge, we use tools and techniques inspired by functional programming. Beyond RTLs, we specialize in creating source codes written in Bluespec SystemVerilog, a vehicle for code correctness, portability and reuse. Atomic Rules provides its clients with expert SoC/FPGA competencies that build upon RTL/ESL design and verification techniques; not reinvent them.

Learn more about Ethernet IP core

Three Ethernet Design Challenges in Industrial Automation

As factories, process plants, and robotics platforms become increasingly intelligent and interconnected, the demand for stable, low-latency data links has pushed Ethernet deeper into embedded systems. However, since designing Ethernet connectivity into industrial chips comes with its technical and logistical hurdles, engineers may face challenges when implementing Ethernet in industrial designs.

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

At the recent ECOC 2025 conference in Copenhagen, Cadence showcased its key role in enabling the future of AI infrastructure with live silicon demonstrations of several essential IP technologies for emerging 800G and 1.6T networks. Powered by Cadence's 224G SerDes IP, Cadence's Ultra Accelerator Link (UALink 1.0) scale-up and Ultra Ethernet scale-out networking solutions deliver the performance, flexibility, and interoperability needed for next-generation AI factories and hyperscale data centers.

Ultra Ethernet Security: Protecting AI/HPC at Scale

As artificial intelligence and high-performance computing (AI/HPC) reshape industries, the need for robust, scalable, and secure connectivity has never been greater. Built from tightly integrated CPUs, GPUs, and SmartNICs, today’s compute clusters demand high-throughput, low-latency networks that can scale from die-to-die to multi-rack deployments.

Frequently asked questions about Ethernet IP cores

What is UDP Offload Engine for IPv4?

UDP Offload Engine for IPv4 is a Ethernet IP core from Atomic Rules LLC listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP