Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component
Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock.
- Timers & Watchdogs
Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component
Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock.
DPDK-aware FPGA/GPP data mover
Arkville provides a high-throughput line-rate agnostic conduit between FPGA hardware and GPP software.
Line-Rate UDP/IPv6 Offload for Modern FPGA Designs UOE6 is Atomic Rules’ next-generation UDP Offload Engine, purpose-built for IP…
Atomic Rules UDP Offload Engine (UOE) is a UDP FPGA IP Core that allows for immediate operation at 10, 25, 40, 50, 100 or 400 GbE.