Vendor: Omni Design Technologies, Inc. Category: DAC

16-bit 5MSPS DAC on TSMC 16 FFC

The ODT-DAC-16B5M-SV-T16 is an ultra-low power, voltage output, 16-bit DAC with a high performance, class AB output buffer.

16 Bit TSMC 16nm FFC View all specifications

Overview

The ODT-DAC-16B5M-SV-T16 is an ultra-low power, voltage output, 16-bit DAC with a high performance, class AB output buffer.

The DAC uses a proprietary architecture that guarantees monotonicity. It also features low glitch, low drift, small area and low power consumption. VSENSE pin is provided to set the load voltage with high accuracy. Both VOUT and VSENSE pins must be routed to the load.

The DAC’s 16-bit parallel interface can be updated at up to 5 MHz on the CLKIN rising edge. When EN_DAC pin is low, the DAC enters a power down mode, where both VOUT and VSENSE pins become high impedance. DAC becomes active when the EN_DAC pin is high.

Key features

  • TSMC 16/12nm FFC
  • 16-bit resolution
  • Single ended, voltage output
  • Rail to rail output buffer
  • 2kΩ // 200pF load drive capability
  • Guaranteed monotonic
  • Low glitch energy
  • Ultra-low current consumption
  • Functional from -40°C to 150°C

Block Diagram

Applications

  • Test and measurement
  • Control loops for telemetry
  • Process control loops
  • Programmable voltage reference
  • Portable devices 

What’s Included?

  • Datasheet
  • Hard Macro (GDSII)
  • Characterization Report (as applicable)
  • Abstract View (LEF) for top level connectivity
  • Spectre Netlist (as needed upon request)
  • Behavioral Model
  • Integration and Customer Support

Silicon Options

Foundry Node Process Maturity
TSMC 16nm FFC

Specifications

Identity

Part Number
ODT-DAC-16B5M-16FFCT
Vendor
Omni Design Technologies, Inc.
Type
Silicon IP

Analog

Resolution bits
16 Bit

Provider

Omni Design Technologies, Inc.
HQ: USA
Omni Design Technologies, Inc. is a developer of disruptive, ultra-low power semiconductor embedded circuits (IP Cores), including ultra-low power analog circuits, highly-efficient interface circuits and connected sensors. Our patented and proprietary technology offers solutions that use dramatically lower power and provide superior performance, architected from the ground up to take advantage of deep sub-micron CMOS processes. Omni Design’s mission is to provide a wide range of ultra low-power, high performance embedded circuits configured to enable highly-differentiated semiconductor systems and plug-and-play system-on-chip (SoC) development. Our IP offerings target SoCs that address a wide range of application areas including IoT, test and measurement, high speed interfaces, communications, medical imaging, and sensor hubs. Omni Design Technologies, Inc. is a privately held company with offices in Milpitas, CA and Boston, MA. Omni Design was founded in 2015 by a team of semiconductor industry veterans, technologists, and experienced entrepreneurs with a successful track record of delivering high performance analog solutions that advance the state of the art.

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 16-bit 5MSPS DAC on TSMC 16 FFC?

16-bit 5MSPS DAC on TSMC 16 FFC is a DAC IP core from Omni Design Technologies, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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