Open SystemC Initiative Announces Completion of New Standard Enabling the Real-World Interoperability of Transaction-Level Models
Much anticipated TLM-2.0 provides essential framework for standards-based ESL design
ANAHEIM, Calif.-- June 09, 2008 -- The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to defining and advancing SystemC™ as an industry-standard language for electronic system-level (ESL) design, today announced the completion of the SystemC Transaction-level Modeling Standard, TLM-2.0. The TLM interface standard enables SystemC model interoperability and reuse at the transaction level, providing an essential ESL framework for architecture analysis, software development, software performance analysis, and hardware verification.
TLM-2.0 focuses on the modeling of systems based on memory-mapped busses and on-chip communication networks. Use cases have been categorized according to a range of criteria, leading to standard interfaces differentiated by loosely-timed (LT) and approximately-timed (AT) modeling styles. More than 2,100 SystemC users and OSCI members participated in the public review, providing feedback on the second draft of the standard since it became available in November 2007. Key changes in TLM-2.0 include new unified interfaces for the LT and AT modeling styles and enhanced support for extended protocol definitions using the generic payload.
"The TLM-2.0 standard represents years of hard work by the OSCI TLM working group, as well as invaluable input from the worldwide SystemC community," said Michael Meredith, President of OSCI. "Based on this level of commitment, OSCI has been able to deliver a robust and stable foundation for transaction-level model interoperability. We are extremely pleased with the result, and the broad industry support TLM-2.0 is enjoying."
Adoption of SystemC TLM is strong and continues to grow worldwide, with companies across the global supply chain taking an active role in promoting standardization efforts. A report issued last year by OSCI noted two interesting trends: the overall increase in demand for SystemC TLM standards fueled by the requirements of a steady mix of ESL design tasks for system level modeling and architecture design, specification and algorithm design, and reference models for functional verification; and new requirements based on rapid growth in the use of SystemC virtual platforms for software development.
"The much anticipated TLM-2.0 standard addresses the real-world interoperability of transaction level models," said Ken Tallo, Director of Virtual Platforms in Intel's SoC Enabling Group. "This will streamline the integration of models from different suppliers without compromising their simulation speed, and allow for continued advances in TLM performance, productivity and usability. Intel has been actively involved in the TLM standardization process and is already working across the ESL ecosystem to incorporate TLM-2.0."
"We are very pleased with the final version of TLM-2.0, which delivers TLM model interoperability while protecting the model provider's freedom to ensure the most appropriate accuracy vs. performance trade-off," said Jean-Marc Chateau, Group Vice President for IP and Design at STMicroelectronics. "TLM-2.0 will be a key enabling technology to speed the integration of the ever-increasing number of models and tools that we use to build the verification and validation platforms for the HW/SW co-development of our most advanced designs. We expect our suppliers to provide TLM-2.0 LT compliant models along with the other usual views of the IP we purchase."
"The system development of new products at an abstract level using SystemC is constantly growing in NXP. It is critical for successful deployment that aspects such as interoperability between models is supported," said Ralph von Vignau, Senior Director at NXP. "Both the use of 3rd party IP, as well as the necessity to design faster, push the requirements for standards providing interoperability. Coupled with the globalization of the electronics market there is also an increasing awareness that interoperability of IP and tools is the way forward. At NXP we believe the TLM-2.0 standard from OSCI addresses these issues and is a big step in the right direction. We are very pleased that it is being released and are already deploying the standard in our company."
Next Steps
OSCI is currently developing a TLM-2.0 language reference manual (LRM) that is planned to be completed by the end of 2008. Designed for use with IEEE Std. 1666™-2005, "Standard SystemC Language Reference Manual" and OSCI's standard TLM-1.0 transport API, the OSCI LRM will be ideally positioned to drive the IEEE standardization process.
Availability
The SystemC TLM-2.0 standard, including library source code implementation, documentation, and examples, is available for download now under open-source license at no cost to users and tool suppliers. To download, visit www.systemc.org.
Quote Sheet
More than 25 companies in the SystemC community – including users, tool, and IP suppliers– have offered quotes demonstrating their support for TLM-2.0 and the work of OSCI. These quotes are available online at www.systemc.org.
About SystemC and OSCI
The Open SystemC™ Initiative (OSCI) is an independent, not-for-profit association composed of a broad range of organizations dedicated to supporting and advancing SystemC as an open industry standard for system-level modeling, design and verification. SystemC is a language built in C++ that spans from concept to implementation in hardware and software. For further information about SystemC and OSCI visit www.systemc.org.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- OCP-IP Develops New Relaxed Commercial Use License for SystemC Transaction Level Modeling Kit
- Calypto Delivers Bus Interface Libraries to Easily Connect High Level Synthesis Models to ARM Platform
- Inside Secure and Intrinsic-ID Team to Bring a New Level of Security to Cloud-Based Transactions
- Aptix "SoC Validation Lab" Taps Zaiq Technologies SYSTEMware™ for Transaction Based Verification and Protocol Support
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers