Synopsys Collaborates with TSMC to Unleash System Innovation with Most Comprehensive Multi-Die Design Solutions for TSMC's Advanced Technologies
Synopsys EDA and IP Solutions Enable New Levels of Integration and Functionality for 2.5D/3D Designs on TSMC's Advanced Process and 3DFabric™ Technologies
MOUNTAIN VIEW, Calif., Oct. 26, 2022 -- Addressing complex customer requirements for heterogeneous compute-intensive applications, Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the industry's most comprehensive EDA and IP solutions for 2D/2.5D/3D multi-die systems for TSMC's most advanced N7, N5 and N3 process technologies. In collaboration with TSMC on its 3DFabric™ technologies and 3Dblox™ standard, Synopsys provides a holistic, system-level approach with production-proven solutions that enables mutual customers to meet the stringent power and performance requirements for complex multi-die systems.
"Synopsys' achievements in multi-die system design technologies complements TSMC's advanced packaging and silicon process technologies in this area, providing our mutual customers with a comprehensive solution for further semiconductor and system-level innovation," said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC. "Together, we are leading the way with differentiated design solutions that will bring to life new applications in AI, high-performance computing, networking, mobile and other key areas."
For more information about Synopsys' 3DIC Multi-Die System solution, visit: https://www.synopsys.com/3dic.html
Why a System-Level Approach Is Critical to Multi-Die Design Success
Key drivers such as cost-effective integration, optimized system cost and performance, lower total power and faster time-to-market are accelerating the shift to multi-die system designs. Compared to their monolithic counterparts, multi-die systems feature a myriad of interdependencies and must be approached holistically from a system perspective. Synopsys EDA tools and IP address all aspects of multi-die systems from architectural partitioning, through silicon/package co-design, to thermal and power management, implementation, verification, software validation, system signoff and silicon lifecycle management.
A key component of the Synopsys solution is the tapeout-proven Synopsys 3DIC Compiler, a unified multi-die co-design and analysis platform that seamlessly integrates with TSMC 3Dblox and TSMC 3DFabric technologies for 3D system integration, advanced packaging and a complete exploration-to-signoff implementation. With 3DIC Compiler, design teams can efficiently bring together dies designed via Synopsys digital and custom design flows certified for TSMC N4P and N3E advanced processes. A broad portfolio of Synopsys IP, including UCIe and HBM3 IP on TSMC's most advanced process technologies, provide high bandwidth and low-power connectivity for multi-die systems.
"Whether it's the high level of integration in heterogeneous compute applications or the challenges of scale and systemic complexities, multi-die systems have emerged as a path forward to enable the next level of system functionality," said Sanjay Bali, vice president of Marketing and Strategy for the EDA Group at Synopsys. "By collaborating closely with TSMC, we are providing the industry's most comprehensive, scalable and trusted EDA and IP solutions that enable designers to accelerate system integration with reduced risk."
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As an S&P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry's broadest portfolio of application security testing tools and services. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products. Learn more at www.synopsys.com.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
- Synopsys and TSMC Streamline Multi-Die System Complexity with Unified Exploration-to-Signoff Platform and Proven UCIe IP on TSMC N3E Process
- Synopsys, TSMC and Ansys Strengthen Ecosystem Collaboration to Advance Multi-Die Systems
- Chiplet Pioneer Eliyan Achieves First Silicon in Record Time with Implementation in TSMC 5nm Process, Confirms Most Efficient Chiplet Interconnect Solution in the Multi-Die Era
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers