Synopsys Launches New ARC VPX DSP Processor IP for High-performance Signal Processing SoC Designs

DesignWare ARC VPX5 and VPX5FS DSP Processors Incorporate Ultra-wide Vector Architecture to Accelerate Highly Parallel Automotive, Sensor Fusion, and Communications Applications

MOUNTAIN VIEW, Calif., Oct. 22, 2019 -- Synopsys, Inc. (Nasdaq: SNPS) today announced the new DesignWare^® ARC^® VPX5 DSP and VPX5FS DSP Processor IP that is based on an extended ARCv2DSP instruction set and optimized for a broad range of high-performance signal processing applications, such as RADAR/LiDAR, sensor fusion, and baseband communications processing. The new ARC VPX5 DSP processors implement a configurable, energy-efficient very long instruction word (VLIW)/single instruction-multiple data (SIMD) architecture that combines scalar and vector execution units to enable a high degree of parallel processing. The Synopsys ARC VPX5FS DSP processor offers safety monitors, lockstep capabilities, and other hardware safety features that help designers achieve the most stringent levels of functional safety and fault coverage without significant impact on power or performance. The ARC VPX5 and VPX5FS DSP processors are supported by the ARC MetaWare Development Toolkit, which provides a comprehensive software programming environment including optimizing vector compiler, debugger, instruction set simulator, and libraries with DSP and math functions.

"We have been impressed by the ARC processor's signal processing performance, which is integrated on top of Arbe's proprietary real-time Radar Processor Unit," said Noam Arkind, founder and chief technology officer at Arbe. "We look forward to the features in the ARC VPX DSP processors that will enable us to further extend our programmable solution coupled with our unique hardware accelerators. Enhancements like linear algebra acceleration and high-performance vector floating point help us develop accurate algorithm implementations."

The ARC VPX5 and VPX5FS processors support single-, dual-, and quad-core configurations. Each VPX core contains a scalar execution unit and multiple vector computation units that support 8-bit, 16-bit, and 32-bit SIMD computations within a 512-bit vector word. The new DSP processors are highly configurable, allowing developers to optimize for power and area by selecting only the hardware features and vector resources needed to meet the required performance level. Neural network algorithms used in machine learning (ML) and artificial intelligence (AI) applications can be efficiently processed by the ARC VPX processors using the 8-bit data type, as well as 16-bit and 32-bit floating point data types.

To address the growing use of floating-point calculations in complex DSP algorithms, up to three vector floating point pipelines are available in each core. The Synopsys ARC VPX5 and VPX5FS support half-, single-, and double-precision floating point data types. Each VPX core also provides dedicated hardware acceleration for linear algebra and math instructions, delivering ultra-high performance for equation-based computations. The ARC VPX DSP processors can deliver 512 FLOPs and 32 math operations per cycle.

To accelerate software development, the Synopsys ARC VPX DSP processors are supported by the ARC MetaWare Development Toolkit with optimizing C/C++ compiler. An auto-vectorization capability enables the compiler to efficiently map all supported floating point and non-floating-point data types onto the respective SIMD execution units with full MAC unit saturation. The compiler is able to efficiently map VLIW operations to all vector computation units, enabling highly parallel execution.

"The tremendous complexity in DSP-intensive algorithms for sensor fusion, LiDAR, and RADAR applications requires higher levels of computation and parallel processing," said John Koeter, vice president of marketing for IP at Synopsys. "By providing a range of high-performance, configurable VPX DSP Processor IP solutions, Synopsys enables designers to address the massive signal processing requirements, while meeting the energy efficiency of their SoCs."

Availability and Resources

• The Synopsys DesignWare ARC VPX5 processor is expected to be available to lead customers in Q1 2020.
• The Synopsys DesignWare ARC VPX5FS processor is expected to be available to lead customers in Q2 2020.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development, and integration of IP into SoCs, Synopsys IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.