Silab Tech Announces Release of XGS-PON SERDES IP Core

Bengaluru, India – June 12th, 2017 – Silab Tech, a leading supplier of high speed serial interface intellectual property designs (IP cores) announced today the release of its XGS-PON PHY. This IP Core provides symmetrical 10Gbps interconnect solution for Next Generation Passive Optical Networks (PON). The IP Core is silicon proven on 40nm node and was integrated successfully into customer chip. The IP was tested on silicon to comply with ITU-T G.9807.1 “10-Gigabit- capable symmetric passive optical network” Standard.

Silab Tech XGS-PON SERDES is compatible with the ONT (Optical Network Termination) as well as OLT (Optical Line Termination). The built-in Burst Mode CDR (Clock Data Recovery) function has a very fast lock time and enable the ONU to quickly align to different PON data rates (1.25/2.5/10Gbps).

Silab Tech XGS-PON is available in 28nm and 40nm silicon technologies – demo board is available upon request.

“Our win into the PON market with XGS-PON SERDES is a great pride for our engineering capabilities. The embedded Low Jitter PLL and Burst Mode CDR are perceived as great value in customers’ eyes” said Ravi Mehta, Silab Tech VP of IP, and added “We are working to continue and develop our PON offering to support the upcoming faster PON Standards.”

Silab Tech will be presenting its XGS-PON and other products at the upcoming DAC-54 Conference (June18-22,2017) in Austin, TX.

About Silab Tech
Silab Tech is a semiconductor IP provider that brings innovative design approaches to the ever-increasing challenge of chip-to- chip and backplane high speed connectivity. The company has a track record of building high speed SERDES IP cores and in integrating them at chip top level. Silab Tech specializes in low power processes and advance nodes. Among the company customers are top multinational semiconductors and fabless IC companies, system companies and ASIC design houses.

For more details on Silab Tech please visit www.silabtech.com