Mentor Graphics Announces Subsystem Intellectual Property Launch with First Delivery of Integrated USB Solution
WILSONVILLE, Ore.-- March 26, 2007 --Mentor Graphics Corporation today announced a technology launch of subsystem intellectual property (IP), beginning with the industry's first USB subsystem solution from a single-source EDA provider. Mentor Graphics is the only EDA company that develops its own digital controller, hardware PHY (physical layer), and embedded software IP to deliver an integrated and verified IP solution for today's complex electronics designs. The end result is faster design creation, improved overall product quality, and faster time-to-market, with particular benefit for the high-demand consumer electronics market.
According to a recent Fabless Semiconductor Association (FSA) discussion on IP ("IP-Building an Efficient Ecosystem," Oct. 11, 2006), third-party IP adopted for today's electronic designs can be costly due to problems encountered with the integration of the digital IP, analog PHY and embedded software IP since these typically come from various IP providers. The FSA discussion indicated that associated costs of identifying, sourcing and verifying semiconductor IP required to create a complete and integrated IP subsystem can greatly impact the total cost of development.
"Mentor is a leader in providing standards-based digital IP and embedded software and verification solutions and we believe that providing a fully integrated and verified subsystem IP solution will support the industry moving forward in 2007," said Kathy Werner, VSI Alliance president. "Mentor's leadership in USB IP provides tremendous advantages for customers developing next-generation products with this offering."
"This past year, many of our large customers have experienced integration issues -- primarily with digital controllers and embedded software IP -- delaying their consumer product introductions. To help remove these integration challenges, we are responding to customer requirements with our Subsystem IP solution," stated Bill Martin, Mentor Graphics IP Division general manager. "As the only EDA company to offer all three technologies -- digital, analog and embedded software IP -- we enable our customers to save critical time and resources with a fully-integrated and verified IP block. Our complete USB Subsystem IP solution removes hidden costs for customers who are faced with the complexities of hardware and software design integration."
USB Subsystem Pricing and Availability
The Mentor Graphics fully-integrated and verified USB Subsystem IP is available now. For more information, go to the company website: www.mentor.com/IP or contact a Mentor Graphics local sales office for specific pricing details. Subsystem IP products presently under development, with availability in 2007, include SATA and Ethernet solutions -- furthering Mentor's technology leadership in these two applications areas.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,250 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Related Semiconductor IP
- USB 3.1 Cable Marker IP
- USB TYPE-C Verification IP
- USB PD Verification IP
- USB 4.0 Verification IP
- USB 3.0/3.1/3.2/SSIC Verification IP
Related News
- Orca Systems Announces the Launch of DRBT, a Dual Mode Bluetooth RF and Modem Intellectual Property (IP) Core
- Cadence Announces the First IP Subsystem with Integrated USB Type-C, USB Power Delivery and DisplayPort Alternate Mode Support
- Intellectual Property Servicing Centre Opens at Hong Kong Science Park; Establishes IP Servicing Platform for the Semiconductor Industry
- Summit Design Launches Intellectual Property Initiative to Enable Consistent, Pre-Verified, Multi-Vendor Compatible IP
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing