Interview: Aart de Geus on AI-driven EDA
By Nitin Dahad, EETimes (March 29, 2023)
At the Synopsys Users Group conference, SNUG 2023, in Santa Clara this week, the company’s chairman and CEO, Aart de Geus, used the keynote speech to talk about the need for AI-driven EDA tools, as Synopsys launched Synopsys.ai, a suite of AI-driven solutions for the design, verification, testing and manufacturing of the most advanced digital and analog chips.
The company said that for the first time, engineers can now use AI at every stage of chip design, from system architecture to design and manufacturing, and access the solutions in the cloud. Renesas, a leader in the automotive space, is already using Synopsys.ai to shave weeks off product development times with enhanced silicon performance and cost reduction.
EE Times has an exclusive video interview with Aart de Geus to talk about the AI-driven EDA, generative AI, talent, and the future of EDA.
Watch the video below:
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
Related News
- EE Times - DAC special: Video interview with Synopsys CEO Aart De Geus
- Synopsys Announces Aart de Geus and Chi-Foon Chan to Become Co-CEOs
- IP99: de Geus calls for core quality
- De Geus IDs trouble spots for system-on-a-chip designs
Latest News
- SEALSQ and IC’Alps Unify Expertise to Deliver Integrated Post-Quantum Cybersecurity and Functional Safety for Autonomous Vehicles
- PUFsecurity’s PUFrt Anchors the Security of Silicon Labs’ SoC to Achieve the Industry’s First PSA Certified Level 4
- The next RISC-V processor frontier: AI
- PQShield joins EU-funded FORTRESS Project: Pioneering Quantum-Safe Secure Boot for Europe’s Digital Future
- PQSecure Achieves NIST CAVP Validation