eSilicon tapes out deep learning ASIC
Chip employs 2.5D/HBM2 technology with TSMC CoWoS® interposer
SAN JOSE, Calif. — September 13, 2017 — eSilicon, an independent provider of FinFET-class ASIC design, custom IP, and advanced 2.5D packaging solutions, today announced the recent successful tapeout for production of a deep learning ASIC. The tapeout marks another significant milestone in eSilicon’s track record of high-performance chips with a 2.5D/high-bandwidth memory (HBM) implementation.
The ASIC includes custom pseudo two-port memories designed by eSilicon, TSMC’s Chip on Wafer on Substrate (CoWoS) technology, 28G SerDes, and four second-generation high-bandwidth memory stacks (HBM2). eSilicon’s end-to-end 2.5D/HBM2 solution includes 2.5D ecosystem management, silicon-proven HBM2 PHY, ASIC physical design, 2.5D package design, manufacturing, assembly and test.
The 2.5D/HBM2 single package implementation gives the ASIC many advantages:
- Orders of magnitude higher total bandwidth in a much smaller board footprint
- Highly parallel connections to memory stacks inside the package for fast access
- Significant reduction in power consumption
“This design pushed the technology envelope and contains many firsts for eSilicon,” said Ajay Lalwani, vice president, global manufacturing operations at eSilicon. “It is one of the industry’s largest chips and 2.5D packages, and eSilicon’s first production device utilizing TSMC’s 2.5D CoWoS packaging technology.”
“TSMC’s CoWoS packaging technology is targeted for the kind of demanding deep learning applications addressed by this design,” said Dr. BJ Woo, TSMC Vice President of Business Development. “This advanced packaging solution enables the high-performance and integration needed to achieve eSilicon’s design goals.”
About eSilicon
eSilicon is an independent provider of complex finFET-class ASIC design, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete, silicon-proven 2.5D/HBM2 and TCAM platforms for finFET technology at 14/16nm. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets.
Related Semiconductor IP
- Simulation VIP for HBM
- HBM Synthesizable Transactor
- HBM DFI Synthesizable Transactor
- HBM Memory Model
- HBM DFI Verification IP
Related News
- ASICs Unlock Deep Learning Innovation: Live Seminar in Silicon Valley
- eSilicon deep learning ASIC in production qualification
- Startup Digs Deep Learning, Snags Big Backers
- Altek License CEVA Imaging and Vision DSP for Deep Learning in Mobile Devices
Latest News
- TSMC Reports First Quarter EPS of NT$13.94
- Thalia joins GlobalFoundries’ GlobalSolutions Ecosystem to advance IP reuse and design migration
- Using UDE® to test virtual automotive RISC-V prototypes from Infineon
- Alphawave Semi Audited Results for the Year Ended 31 December 2024
- ASML targeted in latest round of US tariffs